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Äçìïóéåýóåéò (áðü ôï 1990)
ÐÅÑÉÏÄÉÊÁ
1. N.
Konofaos and G.Ph. Alexiou : "A methodology for the implementation of
MOSFETs with a high-k dielectric gate material on the design of 90 nm
technology circuits", Inter. Journal Of Electronics, 2008, (accepted
for publication).
2. N. Petrelis, N. Konofaos & G.
Ph. Alexiou: "Using future position restriction rules for stabilizing
the results of a noise-sensitive indoor localization system" Optical
Engineering 46(6), 067202, June 2007.
3. N. Konofaos, N. Petrelis & G.
Ph. Alexiou: "Target Localization Utilizing the Success Rate in
Infrared Pattern Recognition", IEEE Sensors Journal, Vol. 6, No 5, Oct
2006, pp 1355-1364.
4. D. Bakalis, M. Bellos, K. Adaos, D. Lymperopoulos, H.
Vergos, G. Alexiou, D. Nikolos: "A core generator for arithmetic cores
and testing structures with a network interface", Journal of System
Architecture, 52 (2006) 1–12.
5. D. Bakalis, E. Kalligeros, D.
Nikolos, H. Vergos and G. Alexiou : "On the design of low power BIST
for multipliers with Both encoding and Wallace tree summation" Journal
of System Architecture,48 (2002) 125-135.
6. D. Bakalis, X Kavousianos,H.
Vergos, D Nikolos, G.P. Alexiou “ Low Power Built-in Self-Test Schemes for
Array and Booth Multipliers” VLSI Design, Vol 12, No 3, pp431-448, 2001.
7. T. Karoubalis, G.Ph. Alexiou, N.
Kanopoulos, “A Dual Rail Circuits Synthesis Environment for the
Implementation of Multiple Output Boolean Functions”, International Journal
of Circuit Theory and Applications, vol. 26, pp. 329-342, 1998.
8. T. Deliyannis, I. Haritantis, G.
Alexiou, C. Psychalinos, A. Limperis
and M. Layos: “A new method for SC
Circuit Synthesis based on the Voltage Inversion Concept”, Journal of Circuits,
Systems and Computers, vol. 6, No1, pp.15-39, Feb. 1996.
9. T. Karoubalis, K. Adaos, G. Ph. Alexiou
and N. Kanopoulos: “A new Efficient
DCV Circuit Synthesis Technique, used for an Improved Implementation of
Serial/Parallel Multiplier”, Inter. Jour.of Circuit Theory and
Applications, vol. 23, 587-598 (1995).
10. G. Alexiou, D. Stiliadis and N.
Kanopoulos: “On the Design of a High Performance, Expandable Sorting
Engine” “Integration: The VLSI Journal”, 18 (1994), pp. 121-135.
11. G. Alexiou and N. Kanopoulos: “A new
Serial/Parallel Multiplier for VLSI Signal Processing” Inter. Jour. of
Circuit Theory and Applications, vol. 20, pp. 209-214, March 1992.
12. N. Bourbakis, M. Papazoglou and G.
Alexiou: “MNT- A Multiprocessor Vision System Architecture” Inter. Journal
of Microprocessors and Microsystems, vol. 14, No 9, pp. 573-581, Nov. 1990.
13. E.Z. Psarakis, B.G. Mertzios and G.
Alexiou: “Design of Two-Dimensional Zero-Phase FIR Fan-Filters via the
McClellan Transform” IEEE Trans. on Circuits and Systems, vol. CAS-37, pp.
10-16, Jan. 1990.
ÂÉÂËÉÁ
1. N. Petrellis, N. Konofaos, G. Ph. Alexiou :"A Sensors System for Indoor
Localisation of A Moving Target Based on Infrared Pattern
Recognition", Scene Reconstruction, Pose Estimation and Tracking,
I-Tech Education and Publishing, Vienna, Austria, pp 283-304, 2007.
ÓÕÍÅÄÑÉÁ
1. Adamopoulou, L., Kordaki, M. and
Alexiou, G.”|The concept of hierarchical design: the views of computer
science and engineering students” Proc. of Informatics Education Europe II
Conference, pp 32-41, IEEII, (ACM),
29-30 November, 2007, Thessaloniki, Greece.
2. N. Petrellis, N. Konofaos and G.Ph.
Alexiou : "Utilising Noise Effects on Infrared Pattern Reception for
Position Estimation on a Grid Plane", Proc. of 12th IEEE Conference on
Emerging Technologies and Factory Automation (ETFA’07), pp 426-433, Patras, GREECE,
Sep 25-28, 2007.
3. N. Petrellis, N. Konofaos and G.Ph.
Alexiou :”A Wireless infrared sensor network for te estimation of the
position and orientation of a moving target”, Mobimedia 2007, Naupaktos, Greece, Aug 2007,
4. V. Mariatos, K. D. Adaos, G. P. Alexiou
:"Design and Implementation of a Reconfigurable, Embedded Real-Time
Face Detection System" Proceedings of 18th IEEE International Workshop
on Rapid System Prototyping (RSP'07), pp. xx-yy, Porto Alegre, Brazil,
May 28-30, 2007.
5. N. Petrellis, N. Konofaos and G.
Ph. Alexiou: "Improving the performance of a position localization
system based on infrared pattern recognition”, Proc of PCI 2007, Patras. GREECE, pp
469-474, May 18-20, 2007.
6. N. Petrellis, N. Konofaos and G.
Ph. Alexiou :"Utilizing infrared pattern recognition features for
indoor localization, validated by future position restrictions” ",
Proc. of 2nd IET International Conference on Intelligent Environments, pp
307-311,5-6 July, Athens, GREECE, 2006.
7. N. Petrellis, N. Konofaos and G.Ph.
Alexiou :"Position Estimation on a Grid, Based on Infrared Pattern
Reception Features", International Workshop on Ubiquitous Computing, Paphos, Cyprus,
May 23, 2006.
8. N. Konofaos, G. Alexiou:
"Modeling and Simulation of Submicron MOSFETs with Alternative Gate
Dielectrics for DRAM Cells", 25th INTERNATIONAL CONFERENCE ON
MICROELECTRONICS, 14-17 May 2006, Belgrade,
Serbia.
9. N. Petrellis, N. Konofaos and G.
Ph. Alexiou: "Testing IR photon sensors for target localization
applications" First International Workshop on Advances in Sensors and
Interfaces,19-20 April 2005, Bari,
ITALY.
10. N. Konofaos, Th. Voilas, G. Ph. Alexiou
: “Design and simulation of an embedded DRAM cell made up with MOSFETs
having alternative gate dielectrics”, SPIE Microtechnologies for the New
Millennium ’05, VLSI Circuits and Systems II. 9-11 May, Sevilla, Spain,
2005.
11. N. Konofaos, Th. Voilas and G. P.
Alexiou, “Effects of unwanted
defects on the reliability and performance of an embedded DRAM cell
designed with MOSFETS with alternative gate dielectrics” 2nd Conference on
Microelectronics Microsystems and Nanotechnology, November 14-17, 2004, Athens,
GREECE. (Best Poster Award)
11. N. Konofaos, G.P. Alexiou, “New challenges emerging on the design of
VLSI circuits made of MOSFETs using new gate dielectric “, Proc. of the 5th
International Symposium on Quality Electronic Design, ISQED 04, pp 92-97,
March 22-24, 2004, San Jose, USA.
13. D. Bakalis, K. D. Adaos, D.
Lymberopoulos, G. Ph. Alexiou and D. Nikolos, "EUDOXUS: A
WWW-based Generator of Reusable Arithmetic Cores", Proceedings of 12th
IEEE International Workshop on Rapid System Prototyping (RSP'01), pp.
182-187, Monterey, CA, USA,
June 25-27, 2001.
14. K.D. Adaos, G.P Alexiou, and N.
Kanopoulos “Development of Reusable Serial FIR Filters with Programmable
Coeficients designed for Serial Dataflow Architectures” Proc. of
ICECS’00, Lebanon, Dec 2000.
15. D. Bakalis, M. Bellos, H. T. Vergos,
D. Nikolos & G. Alexiou “ A Macro Generator for Arithmetic Cores” Proc.
of XV Design of Circuits and
Integrated Systems Conference (DCIS
'2000), November 21–24, 2000.
16. D. Bakalis, E. Kalligeros, D.
Nikolos, H. T. Vergos & G. Ph. Alexiou “Low Power BIST for
WallaceTree-based Fast Multipliers”. Proc. of ISQED 2000, March 20-22,
2000, San Joce, CA, USA.
17. D. Bakalis, H.T. Vergos, D. Nikolos,
X. Kavousianos, G. Ph. Alexiou "A low power BIST scheme for Modified
Booth Multipliers", Proc. of
DFT'99, pp121-129, November 1-3, 1999, Arbuquerque, New Mexico, USA,.
18. A.Vasilliou, K. Gounaris, K. Adaos,
D. Mitsainas, G.Alexiou, and D. Nikolos “Development of a Reusable E1
Transceiver Suitable for Rapid Prototyping” Proc. of RSP’99, pp21-26, June 16-18,USA.
19. K.D. Adaos, G.P Alexiou, and N.
Kanopoulos “Efficient Implementation
of a Serial/Parallel Multiplierfor IP based Development and Rapid
Prototyping of Digital Signal Processing Systems” Proc. of
ICECS’99, pp33-36, Cyprus, Aug 1999.
20. K.D. Adaos, G.P Alexiou, and N.
Kanopoulos “An Extensible, Low Cost, Rapid Prototyping Environment Based on a Re-configurable Set of
FPGAs“ Proc. ïf
RSP’98 , pp78-83, Leuven, Belgium, 3-5 June 1998
21. K .Adaos, K. Platis, M. Perakis, D.
Nikolos and G. Alexiou “FPGA RF Framer/Deframer Unit, An Example of a Specification
Oriented Design” Proc. of DATE ’98, User Forum , pp191-194, Paris, 1998.
22. M. Perakis, K. Platis, K. Adaos,
D.Nikolos, G.Ph. Alexiou & P. Kalnis :”FPGA Implementation of a Sub SDH
STM/1 Framer-Deframer Unit” Proc. of
EMAC ‘97, pp93-96, Barcelona, Spain, 28-30 May, 1997.
23. P. Kalnis, K. Sfiris, G. Ph. Alexiou & D. Nikolos
“From FPGAs to Standard Cell Based VLSI Chip”, Proc of
ED & TC 97, User Forum, pp143-146, Paris, France, 17-20 March,
1997.
24. L. Athanasiou, I.Giouzelis, D.
Nikolos & G. Ph. Alexiou: “FPGA
Implementation of a Protocol Decoder-LCD Driver for a Remotelely Controled
Display System" Proc. of ED
& TC 96, User Forum, pp145-149, Paris, France, 11-14 March, 1996
25. T. Karoubalis, G. Ph.Alexiou, N.
Kanopoulos : "Automatic Synthesis of Differential CVS Circuits for the
Implementation of Multiple Output
Boolean Functions", in Proc. IFIP TC10 International Workshop on Logic
and Architecture Synthesis, pp.119-128, Grenoble, Dec.1995.
26. T. Karoubalis, G. Ph. Alexiou and N. Kanopoulos: "Optimal Synthesis of
Differential Cascode Voltage
Switch (DCVS) Logic Circuits using Ordered binary
decision Diagrams (OBDDs)” in Proc.
of Euro-DAC-95 with Euro-VHDL-95, pp 282-287, Brighton, UK, 1995.
27. G. Alexiou, D. Stiliadis and N.
Kanopoulos "Design and Implementation of a High-Performance, Modular
Sorting Engine" in Proc. of European ASIC, DA & Testing Conference, Vol. 1, pp 2-8, Paris, 1993.
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