Digital Backend Design Engineer - Physical Design ISD S.A. is seeking to employ an ASIC Back-end Design Engineer for digital and/or mixed-signal SoC development in deep sub-micron silicon technologies. The successful candidate will be a talented Engineer with at least 3 years of experience working in advanced technology layout. Experience in the following is required: Experience in the full RTL to GDSII flow, from synthesis to placement. Equivalence checking, STA and IR drop analysis. DFT (ATPG, Scan Insertion). Floor planning. Layout. Signal/power integrity. TCL scripting. Essential: Synopsys Design Compiler for logic synthesis, Cadence Encounter Digital Implementation System for place and route. Desirable: Physical verification tool experience such as Assura, Calibre. CS/EE degree or background in areas related to digital or analog mixed-signal chip design. Submit Your CV here. Copyright © 2015, ISD SA, Integrated Systems Development.