Advanced Topics in Computer Architecture

Course Code: 
CEID_ΝΕ4617
Period: 
Winter Semester
Credit Points: 
5

Course outline

The key topics addressed are:

 Basic principles of 5-stage pipeline

  •  Single-cycle architecture
  • Multi-cycle pipeline architectures

 Analysis of Moore’s law and Dennard’s scaling law

  •  Principal of power consumption in CMOS technology
  •  The transition from unicore to multicore architectures

 Dynamic and speculative instruction execution

  •  Tomasullo algorithm
  •  Static and dynamic branch prediction techniques
  •  Two-level branch predictors (m, n)
  •  Dynamic register renaming
  •  Predication technique
  •  Case studies: Core Duo and Itanium (Intel)

 Hardware level cache based optimizations

  •  Victim caches, pseudo-associative caches, elbow caches
  •  Hardware-software optimizations (replacement strategies, prefetching)
  •  Analysis of the usage of trace cache in hyperthreading architectures

 Compiler level cache optimizations (loop transformations)

 Instruction and data prefetching techniques at the hardware, compiler, and software levels

 Multicore architectures

  • The transition to multicores (ILP wall +power wall+memory wall = multicores)
  •  SISD, SIMD, MISD, MIMD architectures
  •  Shared memory architectures
  •  The cache coherency problem
  •  Directory based and snooping/broadcast protocols
  •  False sharing elimination techniques
  •  Categories and types of multithreaded architectures
  •  The CUDA GPGPU programming model
  •  Memory ordering and memory consistency models (sequential, relaxed, weak consistency models)
  • Memory synchronization through atomic load/stores instructions
  • Other types of parallelism like helper threads, thread level speculation via speculative precomputation and/or run-ahead execution) and transactional memories.

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