Digital Electronics

Course Outline

Α. Lectures and Tutorials

 INTRODUCTION TO DIGITAL ELECTRONICS

• Ideal Logic Gates
• Logic Level Definitions and Noise Margins
• Dynamic Response of Logic Gates
• Review of Boolean Algebra
• NMOS Logic Design
• Transistor Alternatives to the Load
• Resistor
• NMOS Inverter Summary and
• Comparison
• NMOS NAND and NOR Gates
• Complex NMOS Logic Design
• Dynamic Behavior of MOS Logic Gates
• PMOS Logic

 COMPLEMENTARY MOS (CMOS) LOGIC DESIGN

• CMOS Inverter Technology
• Static Characteristics of the CMOS Inverter
• Dynamic Behavior of the CMOS Inverter
• Power Dissipation and Power Delay Product in CMOS
• CMOS NOR and NAND Gates
• Design of Complex Gates in CMOS
• Minimum Size Gate Design and Performance
• Dynamic Domino CMOS Logic
• Cascade Buffers
• The CMOS Transmission Gate
• CMOS Latchup

 MOS MEMORY AND STORAGE CIRCUITS

• Random Access Memory
• Static Memory Cells
• Dynamic Memory Cells
• Sense Amplifiers
• Address Decoders
• Read-Only Memory (ROM)
• Flip-Flops

 BIPOLAR LOGIC CIRCUITS

• The Current Switch (Emitter-Coupled Pair)
• The Emitter-Coupled Logic (ECL) Gate
• Noise Margin Analysis for the ECL Gate
• Current Source Implementation
• The ECL OR-NOR Gate
• The Emitter Follower
•  “Emitter Dotting’’ or “Wired-OR’’ Logic
• ECL Power-Delay Characteristics
• Current Mode Logic
• The Saturating Bipolar Inverter
• A Transistor-Transistor Logic (TTL) Prototype
• The Standard 7400 Series TTL Inverter

B. Lab exercises

Exercise 1: Utilization of measurement devices, operational amplifier circuits (analog IC) with or without controlling resistors, and circuit operation analysis.

Exercise 2: Utilization of measurement devices, characteristics of logic IC families, and their temporal / operational attributes.

Exercise3:  IC featuring flip flops, different types of flip flops, and circuits utilizing flip flops.

Exercise 4: Physical attributes of digital logic IC families.

Exercise 5: Logic IC featuring special attributes, analog IC oscillator, special topics