Part A. Lectures
Basic Knowledge
Elements of digital circuits – Setup and hold time in sequential elements
TTL and CMOS families and their characteristics
Timing info required for a correct design
Design methodologies
- Full-custom design
- Semi-custom design
- Standard-cell design
Design implementation methodologies
- Standard-cell implementation
- Gate – Array, Sea-of-gates, LPGA and FPGA implementation
PCBs and PLDs
PCB manufacturing process
Available chip packages and their relation to available pin count
Packages footprints
Routing layers, line widths, hole diameters and their impact on the PCB cost
Supply and ground layers
What a designer needs to deliver for PCB implementation
PLDs :
- ROMs, FPROMs, EPROMs, EEPROMs and Flash memories
- PALs, PLAs, GALs and FPLSs
- The interconnection problem within a PLD and the solutions provided by CPLDs and FPGAs.
FPGAs
Basic subdesigns : CLBs, IO blocks and programmable interconnect
A close look on the Xilinx 4000 E/EX series FPGAs
The programming of an FPGA or a chain of FPGAs
FPGA size and pin count evolution
Embedded processors, embedded memories and optical transceivers in modern FPGAs. What else should be embedded to achieve System-On-Chip (SoC).
Design flowchart
The need for a flowchart
Front-end and back-end
Front-end design processes: Design entry, logic simulation. Different design entry methods available: graphical, HDL description, macro-block instantiation, FSM based, truth table based, etc.
The back-end design processes depending on the implementation: synthesis and mapping, macro-block generation, flattening, packaging, placement, routing, extraction, back-annotation and timing verification.
The relationship between e-cad tools organization and design flowchart
HDL design entry
- The need for specialized languages
- The difference between an HDL and a programming language
- A short introduction of VHDL
- A thorough presentation of the Verilog HDL