Introduction to VLSI

Course Code: 
CEID_ΝΕ4648
Period: 
Winter Semester
Credit Points: 
5

Course outline

Part A : Lectures

Introduction to CMOS Circuits - Description of the operation of MOS transistors. The CMOS logic. Implementation of gates and simple circuits with CMOS logic: NAND, NOR, gateways, multiplexers and memory. Alternative ways of circuit representation: Behavioral, Structural and Physical. Comparison of CMOS and nMOS technologies. Theoretical analysis and study of MOS transistors. The nMOS enhancement transistor. Threshold voltage and ways of adjusting it.

The body-effect phenomenon. Electrical V-I characteristics of MOS transistors and characteristic equations. Analysis of the time and electrical characteristics of the CMOS inverter, the effect of βn / βp on their configuration and noise margins. Alternative CMOS inverters. Analysis of DC characteristics of the propagation gates. Study the latch-up phenomenon. CMOS-VLSI Circuit Building Technologies - Overview of semiconductor technology. Wafer manufacturing process, Oxidation, Selective diffusion.

The p-well, n-well and twin tub procedures. Improvements and process developments. Design rules. Ways of schematic representation. Lambda-based p-well and SOI rules. Parameterization of the manufacturing process. Circuit characterization and performance estimation - Resistance and capacity calculation. MOS transistor capacities. Diffusion and routing capacities. Design rules for RC effects control.

Time characteristics and design methods for determining: fall time, rise time and delay time. The role of geometric characteristics in determining transistor sizing and transistor (transistor sizing / scaling). Static and dynamic power consumption. The charge-sharing phenomenon. Calculation of yield. CMOS Logic Circuit Design Techniques.

Complementary CMOS, Pseudo-nMOS, Dynamic CMOS, CMOS C2OS, CMOS Domino, CVSL, Modified Domino, Pass Transistor. Design of logic gates (electrical and physical design). Clocking strategies: Pseudo 2-phase, 2-phase, 4-phase, Pseudo-4-phase and recommended approach modes.

Part Β. Laboratoty exercises

The purpose of the lab is to design VLSI logic gates and small circuits. Laboratory exercises are done with the help of specialized design and simulation tools (Cadence)

1. Introduction using an example CMOS inverter (schematic, symbol)

2. Design and simulation of logical gateways: (FCMOS, Domino)

3. Design and simulation of a gate based circuit.

4. Design and simulation of memory circuits.

5. Calculation of VLSI Circuit Function Functions using design and simulation tools.

The lab takes place in the specially designed area of ​​the Microelectronics Laboratory using high resolution terminals and servers that perform specialized commercial software. Contemporary implementation libraries are available to implement the design.

 Licenses for software and libraries are provided by the Pan-European Support Agency of the Europractice Universities.

Conditions: Description of problem and method, Application environment, Communication, Parallel implementation and observations, Analysis of measurements. The laboratory is completed by writing a special report.

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