Digital Design II

Course Code: 
CEID_NY164
Type: 
Semester: 
Credit Points: 
5

Course Outline

Α. Lectures and Tutorials

 Sequential vs combinational circuits

 Synchronous (SSC) and asynchronous sequential circuits

 Sequential components : Latches vs FFs.

  • The instability problem : Setup and hold times
  • Possible implementations of a Dff
  • The rest available kinds of FFs : JK and T FF.
  • Direct inputs (synchronous vs asynchronous) and their implementation
  • The need for scan FFs.
  • D Scan FF.

 

 Mealy and Moore models for synchronous sequential machines. Finite state machines and their representations by state transition diagrams (STDs)

 The correspondence between FSMs and SSCs : The route from SSC to the FSM (SSC analysis) and form the FSM to an SSC (Synthesis of an SSC). The states encoding problem and the choice between a smaller circuit vs that of a safer circuit.

 

 Sequential MSI :

  • Registers (Parallel or serial input and output, load enable, tri-state output)
  • Multi-operation registers
  • Ripple counters
  • Synchronous counters (count enable, parallel load)
  • Designing a specific modulo counter from a binary one.

 

 Verilog HDL descriptions for sequential circuits

  • Sensitivity list of an instruction and aa block of instructions
  • Parallel and serial execution within an instructions block

 Structural and behavioral description of sequential components and circuits.

 Descriptions for simple and multi-operation registers

 Descriptions for counters

 Complete examples for describing and simulating SSCs

 More abstract descriptions : Mealy and Moore FSM descriptions

 

 Semiconductor Memories :

  • ROM  memories : Operation model and architecture. 1-D and 2-D decoding and timing characteristics
  • RAM  memories : Operation model and architecture. SRAM vs DRAM technologies and the refresh cycles in the latter

 Implementation of a combinational circuit by memory programming

 Building a larger memory from smaller ICs.

 Connecting a memory to a microprocessor’s specific address range

 

 Programmable logic devices (PLDs) : ΟTPROMs, E2PROMs, FLASH memory, PLAs, PALs, GALs, CPLDs, FPGAs

Programming a design into a PLD

Β. Laboratory Exercises

Exercise 1

Simple circuits using logic Gates Representation in different codes and translators among them. Arithmetic operations using binary and BCD representations.

Exercise 2

Circuit implementation using arithmetic MSIs (adders and subtractors)

Exercise 3

Implementation of a larger circuit using MSIs and ALUs.

Exercise 4

Counters

Exercise 5

Registers

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