#
# OPTION COMMAND FILE created by Cadence Extraction QRC Version 10.1.2-s123 from CCL
#
capacitance \
	 -decoupling_factor 1.0 \
	 -ground_net "gnd!"
extract \
	 -selection "all" \
	 -type "rc_coupled"
extraction_setup \
	 -array_vias_spacing auto \
	 -max_fracture_length infinite \
	 -max_fracture_length_unit "MICRONS" \
	 -max_via_array_size \
		"auto" \
	 -net_name_space "SCHEMATIC"
filter_cap \
	 -exclude_self_cap true
filter_coupling_cap \
	 -coupling_cap_threshold_absolute 0.01 \
	 -coupling_cap_threshold_relative 0.001
filter_res \
	 -min_res 0.001
input_db -type assura \
	 -design_cell_name "MCBLPREBEQ layout ceid_vlsiLab_umc65ll_memoryCells" \
	 -directory_name "/raid/cadence/LVS_65memCells" \
	 -format "DFII" \
	 -library_definitions_file "/home/simop/cadence/umc65ll_lib/cds.lib" \
	 -run_name "MCBLPREBEQ"
log_file \
	 -file_name "/raid/cadence/LVS_65memCells/qrc.MCBLPREBEQ.log"
output_db -type extracted_view \
	 -cap_component "pcapacitor symbol umc65ll" \
	 -cap_property_name "c" \
	 -enable_cellview_check false \
	 -include_cap_model "false" \
	 -include_parasitic_cap_model "false" \
	 -include_parasitic_res_model "comment" \
	 -include_parasitic_res_width false \
	 -include_parasitic_res_width_drawn false \
	 -include_res_model "false" \
	 -res_component "presistor symbol umc65ll" \
	 -res_property_name "r" \
	 -view_name "extracted"
output_setup \
	 -directory_name "/raid/cadence/LVS_65memCells" \
	 -temporary_directory_name "MCBLPREBEQ"
process_technology \
	 -technology_corner \
		"1P10M2T2F0U_option19" \
	 -technology_library_file "/raid/tools/libraries/umc_65ll/Designkits/Cadence_6.1/assura_tech.lib" \
	 -technology_name "umc65ll_LVS" \
	 -temperature \
		25.0


