Citations

        1. Modulo Adders, Multipliers and Shared-Moduli Architectures for Moduli of Type {2n-1, 2n, 2n+1}, Shibu Menon, Master of Engineering Thesis, School of Electrical and Electronic Engineering, Nanyang Technological University, May 2007.
        2. Contribution to the Study of the Common FFT Operator in Software Radio Context: Application to Channel Coding, A. Al Ghouwayel, Ph.D. Thesis, Universite de Rennes I, Institut d' electronique et de telecommunications de Rennes, Mention : Traitement du Signal et Telecommunications, January 2009.
        3. Κυκλώματα Ύψωσης στο Τετράγωνο για το Σύστημα Αριθμητικής Υπολοίπων, Αν. Σπύρου, Μεταπτυχιακή Διπλωματική εργασία, Τμήμα Μηχανικών Η/Υ & Πληροφορικής, Πανεπιστήμιο Πατρών, Μάϊος 2009.
        4. Modified Overlap Technique using Fermat and Mersenne Transforms, R. Conway, IEEE Transactions on Circuits and Systems II, Vol. 53, No.8, August 2006, pp. 632-636
        5. A One-Step Modulo 2n+1 Adder Based on Double-lsb Representation of Residues, G. Jaberipur, The CSI Journal on Computer Science and Engineering, Vol. 4, No. 2 & 4, 2006, pp. 10-16.
        6. A Residue-to-Binary Converter for a New Five-Moduli Set, B. Cao, C.-H. Chang and T. Srikanthan, IEEE Transactions on Circuits and Systems-I, Vol. 54, No. 5, May 2007, pp 1041-1049.
        7. Low Power Modulo 2n+1 Adder based on Carry Save Diminished-one Number System, S. Timarchi, O. Kavehei and K. Navi, American Journal of Applied Sciences, Vol. 5, No. 4, January 2008, pp. 312-319.
        8. Improved Modulo 2n+1 Adder Design, S. Timarchi and K. Navi, International Journal of Computer and Information Science and Engineering, Vol. 2, No. 3, Summer 2008, pp. 158-165.
        9. VLSI Design of Diminished-One Modulo 2n+1 Adder Using Circular Carry Selection, S.-H. Lin and M.-H. Sheu, IEEE Transactions on Circuits and Systems-II, Vol. 55, No. 9, September 2008, pp. 897-901.
        10. Area-delay Efficient Parallel Architecture for Fermat Number Transform, S. Li and J. Zhang, IEICE Electronics Express, Vol. 6, No. 8, April 2009, pp.449-455.
        11. A New Formulation of Fast Diminished-One Multioperand Modulo 2n+1 Adder, B. Cao, C. H. Chang and T. Srikanthan, IEEE International Symposium on Circuits and Systems (ISCAS 2005), May 23-26, 2005, Kobe, Japan, pp. 656-659.
        12. A Configurable Dual Moduli Multi-Operand Modulo Adder, C.-H. Chang, S. Menon, B. Cao and T. Srikanthan, IEEE International Symposium on Circuits and Systems (ISCAS 2005), May 23-26, 2005, Kobe, Japan, pp. 1630-1633.
        13. Novel VLSI Design of Circular-Carry-Select (CCS) Based Diminished-One Modulo 2n+1 Adder, S.-H. Lin, M.-H. Sheu, K.-H. Wang, J.-J. Zhu and S.-Y. Chen, 18th VLSI Design / CAD Symposium, August 8-10, 2007, Hualian, Taiwan, pp. 13-16.
        14. Complexity Evaluation of a Re-Configurable Butterfly with FPGA for Software Radio Systems, A. Al Ghouwayel, Y. Louet and J. Palicot, 18th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC 2007), September 3-7, 2007, Athens, Greece, pp. 1-5.
        15. New Circular-Carry-Select (CCS) Architecture for Diminished-One Modulo 2n+1 Addition, S.-H. Lin, M.-H. Sheu, Z.-M. Chen, 2007 IEEE Region 10 Conference (TENCON 2007), October 30-November 2, 2007, Taipei, Taiwan, pp. 1-4.
        16. Efficient Residue Arithmetic Based Parallel Fixed Coefficient FIR Filters, R. Conway, IEEE International Symposium on Circuits and Systems (ISCAS 2008), May 18-21, 2008, Seattle, Washington, USA, pp. 1484-1487.
        17. A Low Complexity Modulo 2n+1 Squarer Design, R. Muralidharan, C.-H. Chang and C.-C. Jong, 2008 IEEE Asia Pacific Conference on Circuits and Systems, November 30-December 3, 2008, Macao, China, pp. 1296-1299.
        18. A Fast Low-Power Modulo 2n+1 Multiplier Design, R. Modugu, M. Choi and N. Park, International Instrumentation and Measurement Technology Conference (I2MTC 2009), May 5-7, 2009, Singapore, pp. 951-956.
        19. High Speed Parallel Architecture for Cyclic Convolution Based on FNT, J. Zhang and S. Li, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), May 13-15, 2009, Tampa, Florida, USA, pp.199-204.
        20. Unified Approach to the Design of Modulo-(2n±1) Adders Based on Signed-LSB Representation of Residues, G. Jaberipur and B. Parhami, 19th IEEE Symposium on Computer Arithmetic (ARITH-19), June 8-10, 2009, Portland, Oregon, USA, pp. 57-64.
        21. ELMMA : A New Low Power High-Speed Adder for RNS, R. A. Patel, M. Benaissa, N. Powell and S. Boussakta, IEEE Workshop on Signal Processing Systems (SIPS'04), October 13-15, 2004, Austin, Texas, USA, pp. 95-100.
        22. A Reconfigurable Butterfly Architecture for Fourier and Fermat Transforms, A. Al Ghouwayel, Yves Louet and J. Palicot, 4th Karlsruhe Workshop on Software Radios (WSR'06) , Karlsruhe (Germany), March 22-23, 2006.
        23. The Fastest Modulo 2n±1 Adders, J. Biernat and J. Jablonski, Scientific Reports of the Institute of Engineering Cybernetics, Wroclaw University of Technology, No. 54, 2004.
        24. On the modulo 2n+1 multiplication for diminished-1 operands, C. Efstathiou, I. Voyiatzis and N. Sklavos, 2008 International Conference on Signals, Circuits and Systems, November 7-9, Hammamet, Tunisia, pp. 1-5.
        25. Improved Area-Efficient Weighted Modulo 2n+1 Adders Design with Simple Correction Schemes, T.-B.  Juang, C.-C. Chiu and M.-Y. Tsai, IEEE Transactions on Circuits and Systems II, to appear.
        26. Variation-Tolerant Design using Residue Number System, I. Kouretas and V. Paliouras, 12th Euromicro Conference on Digital System Design (DSD 2009), Patras, Greece, August 27-29, 2009, pp. 157-163.
        27. Design and Implementation of Area-Efficient Weighted Modulo 2n+1 Multipliers, T.-B. Juang, K.-L. Wu and C.-C. Chiu, Proc. of the Taiwanese Symposium on System Prototyping, Circuit Design and Innovation, Taipei, Taiwan, October 10-16, 2009, pp. 376-381.