Citations

1. "On-Line Testing of IP-Based Systems via Selectively Transparent Scan", H. Kim and J.P. Hayes, 5th IEEE Int. On-Line Testing Workshop, pp. 138-142, 1999.
2. "Delay Fault Testing of IP-Based Designs via Symbolic Path Modeling", H. Kim and J.P. Hayes, IEEE Transactions on VLSI Systems, vol. 9, no. 5, pp. 661-678, 2001.
3. "Testing and Synthesis of Systems-on-a-Chip with Unimplemented Blocks", H. Kim, Ph.D. Thesis, Electrical Engineering Dept., University of Michigan, 1999.
4. "Efficient Path Delay Test Generation for Custom Designs", S. Kang, B. Underwood, W-O. Law and H. Konuk, Electronics and Telecommunication Reserch Institute Journal, vol. 23, no. 3, pp. 138-149, 2001.
5. Delay Fault Testing of Designs with Embedded IP-Cores, H. Kim and J. P. Hayes, 17th IEEE VLSI Test Symposium (VTS '99), April 25-29, 1999, Dana Point, CA, USA, pp. 160-167.
6. Delay Fault Testing of IP-Based Designs via Symbolic Path Modeling, H. Kim and J. P. Hayes, IEEE International Test Conference (ITC '99), September 28-30, 1999, Washington DC, USA, pp. 1045-1054.
7. Aναφέρεται στο web site http://grouper.ieee.org/groups/1500/bib/ με τη βιβλιογραφία που αφορά τις δραστηριότητες της ομάδας της Test Technology Technical Council (TTTC) της IEEE Computer Society η οποία ήταν επιφορτισμένη με την ανάπτυξη του IEEE P1500 standard on the Testing of Embebbed Core Systems, (E.J. Marinissen - Philips Microelectronics), Oct. 1999.