Citations

        1. Residue Number Systems: Algorithms and Architectures, P. V. Ananda Mohan, Kluwer Academic Publishers, 2002.
        2. Residue Number Systems Theory and Implementation, A. Omondi and B. Premkumar, Imperial College Press, 2007.
        3. Modelo Parametrico de Arquitectura para la Generacion de Primitivas Computacionales, M. T. S. Pont, Departamento de Tecnologia Informatica y Computacion, Universidad de Alicante, May 2005.
        4. Μονάδες Επεξεργασίας Δεδομένων για Επεξεργαστές Υψηλών Επιδόσεων, Γ. Δημητρακόπουλος, Διδακτορική Διατριβή, Τμήμα Μηχανικών Η/ Υ & Πληροφορικής, Πανεπιστήμιο Πατρών, Φεβρουάριος 2007.
        5. Modulo Adders, Multipliers and Shared-Moduli Architectures for Moduli of Type {2n-1, 2n, 2n+1}, Shibu Menon, Master of Engineering Thesis, School of Electrical and Electronic Engineering, Nanyang Technological University, May 2007.
        6. Algorithmes Paralleles Auto-Adaptatifs et Applications, D. Traore, Ph. D. Thesis, L' Ecole Doctorale "Mathematiques, Sciences et Technologies de l'Information, Informatique", L' Institut Polytechnique de Grenoble, January 2009.
        7. Contribution to the Study of the Common FFT Operator in Software Radio Context: Application to Channel Coding, A. Al Ghouwayel, Ph.D. Thesis, Universite de Rennes I, Institut d' electronique et de telecommunications de Rennes, Mention : Traitement du Signal et Telecommunications, January 2009.
        8. Κυκλώματα Ύψωσης στο Τετράγωνο για το Σύστημα Αριθμητικής Υπολοίπων, Αν. Σπύρου, Μεταπτυχιακή Διπλωματική εργασία, Τμήμα Μηχανικών Η/Υ & Πληροφορικής, Πανεπιστήμιο Πατρών, Μάϊος 2009.
        9. Residue Number System to Binary Converter for the Moduli Set (2n-1, 2n-1, 2n+1), A. Hiasat and A. Sweidan, Journal of Systems Architecture, Vol. 49, No. 1-2, July 2003, pp. 53-58.
        10. Residue-to-binary Decoder for an Enhanced Moduli Set, A. Hiasat and A. Sweidan, IEE Proceedings-Computers and Digital Techniques, Vol. 151 , No. 2, March 2004, pp. 127-130.
        11. Coding Techniques for Fault-Tolerant Parallel Prefix Computations in Abelian Groups, C. N. Hadjicostis, The Computer Journal, Vol. 47, No. 3, May 2004, pp. 329-340.
        12. VLSI Implementation of New Arithmetic Residue to Binary Decoders, A. A. Hiasat, IEEE Transactions on VLSI Systems, Vol. 13, No. 1, January 2005, pp. 153-158.
        13. Processing Society of Japan Journal, Vol. 46, No. 12, December 2005, pp. 3030-3039.
        14. New Booth Modulo m Multipliers with Signed-Digit Number Arithmetic, S. Chen and S. Wei, Information and Media Technologies, Vol. 1, No. 1, 2006, pp. 212-221 .
        15. Performance Evaluation of Signed-Digit Architecture for Weighted-to-Residue and Residue-to-Weighted Number Converters with Moduli Set (2n-1, 2n, 2n+1), S. Chen and S. Wei, Information Processing Society of Japan Journal, Vol. 47, No. 6, June 2006, pp. 328-337.
        16. Performance Evaluation of Signed-Digit Architecture for Weighted-to-Residue and Residue-to-Weighted Number Converters with Moduli Set (2n-1, 2n, 2n+1), S. Chen and S. Wei, Information and Media Technologies Vol. 1, No. 2, 2006, pp. 899-908.
        17. Modified Overlap Technique using Fermat and Mersenne Transforms, R. Conway, IEEE Transactions on Circuits and Systems II, Vol. 53, No.8, August 2006, pp. 632-636.
        18. Modulo (2p±1) Multipliers using a Three-operand Modular Signed-Digit Addition Algorithm, S. Wei and K. Shimizu, Journal of Circuits, Systems and Computers, Vol. 15, No. 1, January 2006, pp. 129-144.
        19. Efficient New Approach for Modulo 2n-1 Addition in RNS, R. A. Patel, M. Benaissa and S. Boussakta, IEE Proceedings, Computers and Digital Techniques, Vol. 153, No. 6, November 2006, pp. 399-405.
        20. A One-Step Modulo 2n+1 Adder Based on Double-lsb Representation of Residues, G. Jaberipur, The CSI Journal on Computer Science and Engineering, Vol. 4, No. 2 & 4, 2006, pp. 10-16.
        21. A Fast Algorithm for RNS-to-Binary Conversion, S. Chen and S. Wei, WSEAS Transactions on Computers, Vol. 6, No. 5, May 2007, pp. 733-740.
        22. Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero, R. A. Patel, M. Benaissa and S. Boussakta, IEEE Transactions on Computers, Vol. 56, No. 11, November 2007, pp. 1484-1492.
        23. A New High Dynamic Range Moduli Set with Efficient Reverse Converter, A. Hariri, K. Navi and R. Rastegar, Computers and Mathematics with Applications, Vol. 55, No. 4, February 2008, pp. 660-668.
        24. Area-Time Efficient Modulo 2n-1 Adder Design Using Hybrid Carry Selection, S.-H. Lin and M.-H. Sheu, IEICE Transactions on Information and Systems, Vol. E-91-D, No. 2, February 2008, pp. 361-362.
        25. An Efficient Architecture for Designing Reverse Converters Based on a General Three-Moduli Set, A. S. Molahosseini, K. Navi, O. Hashemipour and A. Jalali, Journal of Systems Architecture, Vol. 54, No.10, October 2008, pp.929-934.
        26. The Mixed-Radix Chinese Remainder Theorem and Its Applications to Residue Comparison, S. Bi and J. Warren, IEEE Transactions on Computers, Vol. 57, no. 12, December 2008, pp.1624-1632.
        27. Practical High-Throughput Crossbar Scheduling, N. Chrysos and G. Dimitrakopoulos, IEEE Micro, vol. 29, No. 4, July-August 2009, pp. 22-35.
        28. A New RNS to Mixed-Radix Number Converter using Modulo (2p-1) Signed-Digit Arithmetic, S. Wei and K. Shimizu, IEEE Asia-Pacific Conference on Circuits and Systems, December 6-9, 2004, Tainan, Taiwan, pp. 377-380.
        29. A New Design Method to Modulo 2n-1 Squaring, B. Cao, T. Srikanthan and C. H. Chang, IEEE International Symposium on Circuits and Systems (ISCAS 2005), May 23-26, 2005, Kobe, Japan, pp. 664-667.
        30. A Configurable Dual Moduli Multi-Operand Modulo Adder, C.-H. Chang, S. Menon, B. Cao and T. Srikanthan, IEEE International Symposium on Circuits and Systems (ISCAS 2005), May 23-26, 2005, Kobe, Japan, pp. 1630-1633.
        31. Bipartite Implementation of the Residue Logarithmic Number System, M. G. Arnold and J. Ruan, International Symposium on Optical Science and Technology, Conference 5910-Computer Arithmetic I, SPIE Annual Meeting, August 3, 2005, San Diego, California, pp. 1-9.
        32. Number Conversions between RNS and Mixed-Radix Number System based on Modulo (2p-1) Signed-Digit Arithmetic, S. Wei, 18th Symposium on Integrated Circuits and System Design, Florianolpolis, Brazil, Septemeber 4-8, 2005, pp. 160-165.
        33. Weighted-to-Residue and Residue-to-Weighted Converters with Three-Moduli (2n-1, 2n, 2n+1) Signed-Digit Architectures, S. Chen and S. Wei, IEEE International Symposium on Circuits and Systems (ISCAS 2006), May 21-24, 2006, Kos, Greece, pp. 3365-3368.
        34. High-Speed Redundant Modulo 2n-1 Adder, F. Kharbash, G. M. Chaudhry, 4th ACS/IEEE International Conference on Computer Systems and Applications (AICCSA 2006), March 8-11, 2006, Sharjah, UAE pp. 80-87.
        35. A High-Speed Realization of Chinese Remainder Theorem, S. Chen and S. Wei, WSEAS International Conference on Circuits, Systems, Signal and Telecommunications, January 17-19, 2007, Gold Coast, Australia, pp. 97-102.
        36. A Multiplicative Inverse Algorithm Based on Modulo (2p-1) Signed-Digit Arithmetic for Residue to Weighted Number Conversion, S. Wei, IEEE International Symposium on Integrated Circuits (ISIC '07), September 26-28, 2007, Singapore, pp. 1-4.
        37. A New Residue to Binary Converter Based on Mixed-Radix Conversion, A. S. Molahosseini, K. Navi and M. K. Rafsanjani, 3rd International Conference on Information and Communication Technologies (ICTTA 2008), April 7-11, 2008, Damascus, Syria, pp. 1-6.
        38. Efficient Residue Arithmetic Based Parallel Fixed Coefficient FIR Filters, R. Conway, IEEE International Symposium on Circuits and Systems (ISCAS 2008), May 18-21, 2008, Seattle, Washington, USA, pp. 1484-1487.
        39. Fast Arbitrers for On-Chip Network Switches, G. Dimitrakopoulos, N. Chrysos and K. Galanopoulos, 26th IEEE International Conference on Computer Design, (ICCD 2008), October 12-15, 2008, Lake Tahoe, California, USA, pp. 664-670.
        40. Modular Multipliers Using a Modified Residue Addition Algorithm with Signed-Digit Number Representation, S. Wei, International Multiconference of Engineers and Computer Scientists (IMECS 2009), March 18-20, 2009, Hong Kong, Vol. I, pp. 494-499.
        41. Efficient VLSI Design of a Reverse RNS Converter for New Flexible 4-Moduli Set (2p+k, 2p+1, 2p-1, 22p+1), Y.-C. Kuo et. al., 2009 International Symposium on Circuits and Systems (ISCAS-2009), 24-27 May 2009, Taipei, Taiwan, pp. 437-440.
        42. Fixed and Variable Multi-Modulus Squarer Architectures for Triple Moduli Base of RNS, R. Muralidharan and C. -H. Chang, 2009 International Symposium on Circuits and Systems (ISCAS-2009), 24-27 May 2009, Taipei, Taiwan, pp. 441-444.
        43. Unified Approach to the Design of Modulo-(2n±1) Adders Based on Signed-LSB Representation of Residues, G. Jaberipur and B. Parhami, 19th IEEE Symposium on Computer Arithmetic (ARITH-19), June 8-10, 2009, Portland, Oregon, USA, pp. 57-64.
        44. Parallel-Prefix Ling Structures for Modulo 2n-1 Addition, J. Chen and J. Stine, 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 09), July 7-9, 2009, Boston MA, USA, pp. 16-23.
        45. An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction, S. Bi, W. J. Gross, W. Wang, A. Al-Khalili and M. N. S. Swamy, 5th International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), Banff, Alberta, Canada, July 20 -24, 2005, pp. 396-399.
        46. Efficient VLSI Design of Modulo 2n-1 Adder using Hybrid Carry Selection, S.-H. Lin, M.-H. Sheu, K.-H. Wang, J.-L. Zhu and S.-Y. Chen, IEEE Workshop on Signal Processing Systems, Shanghai, China, October 17-19, 2007, pp. 142-145.
        47. A New Residue Adder with Redundant Binary Number Representation, S. Wei, Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA), Toulouse, France, June 28-July 1, 2008, pp. 157-160.
        48. The Fastest Modulo 2n±1 Adders, J. Biernat and J. Jablonski, Scientific Reports of the Institute of Engineering Cybernetics, Wroclaw University of Technology, No. 54, 2004.
        49. A High Dynamic Range 3-Moduli-Set with Efficient Reverse Converter, A. Hariri, R. Rastegar, K. Navi, Cornell University, Report No. 0901.1123, January 2009.
        50. Design of Cost-Efficient Multipliers Modulo 2a-1, S. Piestrak, 2010 International Symposium on Circuits and Systems (ISCAS-2010), May 30 - June 2, 2010, to appear.