Citations

  1. "Low-Cost On-Line Test for Digital Filters", I. Bayraktaroglu and A. Orailoglu, 17th IEEE VLSI Test Symposium, Dana Point , California, April 25-29, 1999, pp. 446-451.
  2. "Compined On-Line/Off-Line Test Solutions for Digital Filters", I. Bayraktaroglu and A. Orailoglu, 5th IEEE Int. On-Line Testing Workshop, 1999.
  3. "Unifying methodologies for high fault coverage concurrent and off-line test of digital filters", Bayraktaroglu, I, Orailoglu, A, in Proceedings of the 2000 IEEE International Symposium on Circuits and Systems, Geneva, Switzerland, 28-31 May 2000, 2000. pp.705-708.
  4. "Invariance-Based On-Line Test for RTL Controller-Datapath Circuits", Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu  Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00), 2000
  5. "Cost effective digital filter design for concurrent test", Bayraktaroglu, I., Orailoglu, A., Proceedings. 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2000. ICASSP '00.
  6. "Test Requirement Analysis for Low Cost Hierarchical Test Path Construction," Y. Makris, A. Orailoglu, Proceedings of the IEEE Asian Test Symposium (ATS), pp.134-139, 2002
  7. "Non-intrusive design of concurrently self-testable FSMs", Drineas, P., Makris, Y., Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).
  8. "SPaRe: Selective Partial Replication for Concurrent Fault-Detection in FSMs", Drineas, P., Makris, Y. IEEE Transactions on Instrumentation and Measurement, 52 (6), pp. 1729-1737, 2003
  9. "Concurrent fault detection in random combinational logic", Drineas, P.; Makris, Y., Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, Vol., Iss., 24-26 March 2003, pp. 425- 430
  10. "Design of concurrent test hardware for linear analog circuits with constrained hardware overhead", Ozev, S., Orailoglu, A. , IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12 (7), pp. 756-765, 2004
  11. "Enhancing reliability of RTL controller-datapath circuits via invariant-based concurrent test", Makris, Y., Bayraktaroglu, I., Orailoglu, A.,  IEEE Transactions on Reliability, 53 (2), pp. 269-278., 2004
  12. "Concurrent error detection for combinational and sequential logic via output compaction", Almukhaizim, S., Drineas, P., Makris, Y., Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004, pp. 459-464, 2004
  13. "Compaction-based concurrent error detection for digital circuits", Almukhaizim, S., Drineas, P., Makris, Y., Microelectronics Journal, 36 (9), pp. 856-862., 2005
  14. "ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs," Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, ats, pp. 195-202,  15th Asian Test Symposium (ATS'06),  2006.
  15. "RT level reliability enhancement by constructing dynamic TMRS", N Karimi, S Mirkhani, Z Navabi, F Lombardi, Proceedings of the 17th great lakes symposium on VLSI, pp. 172 - 175, 2007
  16. "On the identification of modular test requirements for low cost hierarchical test path construction",Yiorgos Makris, Alex Orailoglu, INTEGRATION, the VLSI journal 40 (2007) 315-325