Citations

  1. From Specification to Embedded Systems Application, IFIP International Federation for Information Processing Book Series, Volume 184/2005, Book Chapter : TOC-BISR: A Self-Repair Scheme for Memories in Embedded Systems, G. Neuberger, F. L. Kastensmidt and R. Reis, Springer Boston, 2005.
  2. Fault-Tolerant Computing for Radiation Environments, P. P. Shirvani, Ph.D. Thesis, Department of Electrical Engineering and Computer Science, Stanford University, July 2001.
  3. Active Management of Cache Resources, S. Ramaswamy, Ph. D. Thesis, School of Electrical and Computer Engineering, Georgia Institute of Technology, Aug 2008.
  4. Process Variation in Embedded Memories : Failure Analysis and Variation Aware Architecture, A. Agarwal, B. C. Paul, S. Mukhopadhyay and K. Roy, IEEE Journal of Solid State Circuits, Vol. 40, No. 9, September 2005, pp. 1804-1813.
  5. A Code Placement Technique for Improving the Performance Yield of Processors with Defective Caches, T. Ishihara and F. Fallah, IEICE Technical Reports, Vol. 105, No. 350, 2005, pp. 61-66.
  6. Fault Tolerant Cache Schemes, H.-Y. Tu and S. Tasneem, Advances in Computational Algorithms and Data Analysis, Lecture Notes in Electrical Engineering, Vol. 14, September 2008, S.-I. Ao, B. Rieger and S.-S. Chen (eds), Springer-Verlag, pp. 99-115.
  7. PADded Cache : A New Fault-Tolerance Technique for Cache Memories, P. P. Shirvani and E. J. McCluskey, 17th IEEE VLSI Test Symposium (VTS '99), April 25-29, 1999, Dana Point, CA, USA, pp. 440-445.
  8. A Cache-Defect-Aware Code Placement Algorithm for Improving the Performance of Processors, T. Ishihara and F. Fallah, IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2005), San Jose, CA, USA, November 6-10, 2005, pp. 995-1001.
  9. Re-Evaluation of Fault Tolerant Cache Schemes, H.-Y. Tu and S. Tasneem, World Congress on Engineering and Computer Science (WCECS 2007), October 24-26, 2007, San Francisco, USA, pp. 252-258.
  10. Non-FPGA-Based Field-Programmable Self-Repairable (FPSR) Microarchitecture, Y.-K. Jung, NASA/ESA Conference on Adaptive Hardware and Systems (AHS'08), June 22-25, 2008, Noordwijk, The Netherlands, pp. 93-100.
  11. A Code Placement Technique for Improving the Performance of Processors with Defective Caches, T. Ishihara and F. Fallah, 14th International Workshop on Logic and Synthesis (IWLS 2005), June 8-10, 2005, Lake Arrowhead, California, USA, pp. 210-214.
  12. PADded Cache : A New Fault-Tolerance Technique for Cache Memories, P. P. Shirvani and E. J. McCluskey, Center for Reliable Computing, Department of Electrical Engineering and Computer Science, Stanford University, Technical Report No CSL TR#00-802, December 2000.
  13. Fault-Tolerant Computing for Radiation Environments, P. P. Shirvani and E. J. McCluskey, Center for Reliable Computing, Department of Electrical Engineering and Computer Science, Stanford University, Technical Report No CSL TR#01-601, June 2001.
  14. A Code Placement Technique for Improving the Performance Yield of Processors with Defective Caches, F. Fallah and T. Ishihara, Kyoshu University Institutional Repository, Technical Report No. 102, 2005, pp. 179-184.