Citations

  1. Arithmetic Built-In Self-Test for Embedded Systems", J. Rajski and J. Tyszer, Kluwer Academic Publishers, 1997.
  2. "Test Response Compaction Using Arithmetic Functions", A.P. Stroele, 14th VLSI Test Symposium, 1996, pp. 380-386.
  3. "Mixed-Mode BIST Using Embedded Processors", S. Hellebrand, H-J. Wunderlich, A. Hertwig, IEEE International Test Conference 1996, pp. 195-204.
  4. "On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs", C. Dufaza and Y. Zorian, European Design & Test Conference 1997, pp. 69-76.
  5. "Test Generator for Detecting Sequential Faults", R.K. Latypov, Automated Remoted Control, vol. 58, part 2, June 1997, pp. 1044-1049.
  6. "BIST Pattern Generators Using Addition and Subtraction Operations", A. Stroele, JETTA, vol. 11, Aug. 1997, pp. 69-80.
  7. "Mixed-Mode BIST Using Embedded Processors", S. Hellebrand, H.J. Wunderlich and A. Hertwig, Journal of Electronic Testing. Theory and Applications (JETTA), vol. 12, no. 1/2, Feb./Apr. 1998, pp. 127-138.
  8. "Theoretical Properties of LFSRs for Bult-In Self-Test", C. Dufaza,Integration: the VLSI Journal, vol. 25, Sept. 1998, pp. 17-35.
  9. "Exploiting BIST approach for two-pattern testing", Xiaowei Li; Cheung, P.Y.S. Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian, Vol., Iss., 2-4 Dec 1998 Pages:424-429
  10. "Application-Dependent Testing of FPGA Delay Faults," Andrzej Krasniewski,  Euromicro, p. 1260,  25th Euromicro Conference (EUROMICRO '99)-Volume 1,  1999.
  11. "Exploiting Deterministic TPG for Path Delay Testing", X.W. Li, PYS. Cheung, Journal of Computer Science Technology, vol. 15, Sep. 2000, pp. 472-479.
  12. "Synthese effizienter Testmustergeneratoren fur den deterministischen funktionalen Selbsttest", R. Dorsch, H.-J. Wunderlich, 12th GI/ITG/GMM/IEEE Workshop "Testmethoden und Zuverlassigkeit von Schaltungen und Systemen", Grassau, Session 4, pp. 1-7, March 19-21, 2000
  13. "Selbsttest mit Akkumulatoren", Mayer, F. PhD Thesis, University of Carlsruhe, 2000
  14. LFSR-based Deterministic TPG for Two-Pattern Testing, X.W. Li, PYS. Cheung, H. Fujiwara, Journal of Electronic Testing. Theory and Applications (JETTA), vol. 16, Oct. 2000, pp. 419-426.
  15. "A novel solution for testing power and testing time", L Xu, Y Sun, H Chen - ASIC, 2001. Proceedings. 4th International Conference on ASIC, 2001
  16. "Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation", Kazuteru NAMBA , and Hideo ITO, IEICE Trans Inf & Syst E88-D: 2135-2142, 2005