Citations

    1. "Novel Implementation for Highly Testable Parity Code Checkers"", C. Metra M. Favali and B. Ricco, Proc. of 4th IEEE Int. On-Line Testing Workshop 1998, pp. 167-171.
    2.  "Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Codes", Albrecht P Stroele, Steffen Tarnick,  17th IEEE VLSI Test Symposium, Dana Point , California, April 25-29, 1999, pp. 361-369.
    3. "Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes", STEFFEN TARNICK, JOURNAL OF ELECTRONIC TESTING: Theory and Applications 16, pp.355-367, 2000
    4. "Concurrent Fault Detection in Random Combinational Logic," Petros Drineas, Yiorgos Makris, Fourth International Symposium on Quality Electronic Design, International Symposium, San Jose, California, March 24-26, 2003, pp. 425
    5. "Embedded Self-Testing Checkers for Low-Cost Arithmetic Codes", Steffen Tarnick, Albrecht P. Stroele,, International Test Conference 1998 (ITC'98), 1998. , pp. 514.
    6. "Ultra fast and low cost parallel two-rail code checker targeting high fan-in applications", Matakias, S.   Tsiatouhas, Y.   Haniotakis, Th.   Arapoyanni, A.   Proceedings. IEEE Computer society Annual Symposium on VLSI, 2004, Feb. 19-20, 2004,pp. 293- 296.
    7. "Fast, parallel two-rail code checker with enhanced testability", Matakias, S.   Arapoyanni, A.   Efthymiou, A.   Tsiatouhas, Y.   Haniotakis, T. 11th IEEE International On-Line Testing Symposium, July 6-8,  2005. IOLTS 2005.  pp. 149- 156.
    8. "Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers", HAO-YUNG LO, HSIU-FENG LIN, CHICHYANG CHEN, JENSHIUH LIU AND CHIA-CHENG LIU, JOURNAL OF ELECTRONIC TESTING: Theory and Applications 19, 245-269, 2003
    9. "Single- and Double-Output Embedded Checker Architectures for Systematic Unordered Codes, STEFFEN TARNICK, JOURNAL OF ELECTRONIC TESTING: Theory and Applications 21, 391-404, 2005.
    10. "A novel self-routing reconfigurable fault-tolerant cell array", Xiaoxuan She   Zwolifiski, M.., Second NASA/ESA Conference on Adaptive Hardware and Systems, 2007. AHS 2007,  5-8 Aug. 2007, pp. 725-731
    11. "Self-routing, reconfigurable and fault-tolerant cell array", X. She,  IET Comput. Digit. Tech., 2008, Vol. 2, No. 3, pp. 172-183
    12. "A Current Mode, Parallel, Two-Rail Code Checker", Matakias, S.   Tsiatouhas, Y.   Haniotakis, T. Arapoyanni, A., IEEE Transactions on Computers,  Aug. 2008, pp. 1032-1045.
    13. "On the Design of Self-Checking Controllers with Datapath Interactions", Oikonomakos, P.   Zwolinski, M., IEEE Transactions on Computers, Volume: 55,  Issue: 11,  Nov. 2006, pp. 1423-1434.