Citations

1. "A Novel High Speed Sense Amplifier for Bi-NOR Flash Memories", C-C. Chung, H. Lin, and Y-T. Lin, IEEE Journal of Solid-State Circuits, vol. 40, no. 2, pp. 515-522, 2005.
2. "Error Protected Ternary Content-Addresable Memories and Lookup Operations Performed Thereon", S. Krishnan, R. Panigrahy and S. Parthasarathy, United States Patent, pn. US 7,345,897 B2, dp. Mar. 18, 2008.
3. "Associative Memory Cells Configured to Selectively Produce Binary or Ternary Content-Addressable Memory Lookup Results", S. Parthasarathy and S. Krishnan, United States Patent, pn. US 7,349,230 B2, dp. Mar. 18, 2008.
4. "False Error Study of On-Line Soft Error Detection Mechanisms", K. Reddy, B. Amrutur and R. Parekhji, 14th IEEE Int. On-Line Testing Symposium (IOLTS), pp. 53-58, 2008.
5. "A Built-In Self Test Scheme for Soft Error Rate Characterization", A. Sanyal, S. Alam and S. Kundu, 14th IEEE Int. On-Line Testing Symposium (IOLTS), pp. 65-70, 2008.
6. "Error-Correcting Codes for Ternary Content Addresable Memories", S. Krishnan, R. Panigrahy and S. Parthasarathy, IEEE Transactions on Computers, vol. 58, no. 2, pp. 275-279, 2009.
7. "Design and Analysis Methodologies to Reduce Soft Errors in Nanometer VLSI Circuits", Balkaran Singh Gill, Case Western Reserve University (USA), Ph.D. Thesis, Jun. 2006.