Citations

1. S. Manich, L. Garcia, L. Balado, E. Lupon, J. Rius, R. Rodriguez & J.Figueras, "BIST technique by equally spaced test vector sequences",  in Proc. of the 22nd IEEE VLSI Test Symposium, April 2004.
2. Salvador Manich, Lucas Garcia, and Joan Figueras, Minimizing Test Time in Arithmetic Test Pattern Generators with Constrained Memory Resources, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 26, no. 11, pp. 2046-2058, November 2007