Citations

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  2. M. Nourani, M. Tehranipoor and N. Ahmed, "Low-Transition Test Pattern Generation for BIST-based Applications", IEEE Transactions on Computers, vol. 57, no. 3, pp. 303-315, March 2008.
  3. S. Chun, T. Kim and S. Kang, "A New Low Energy BIST Using a Statistical Code", Proc. of  Asia and South Pacific Design Automation Conference (ASPDAC), pp. 647-652, March 2008.
  4. S. Udar and D. Kagaris, "LFSR Reseeding with Irreducible Polynomials", Proceedings of 13th IEEE Int. On-Line Testing Symposium (IOLTS), pp. 293-298, July 2007.
  5. N.-C. Lai, S.-J Wang and Y.-H. Fu, "Low-Power BIST with a Smoother and Scan-Chain Reorder under Optimal Cluster Size", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp. 2586-2594, November 2006.
  6. N.-C. Lai, S.-J Wang and Y.-H. Fu, "Low Power BIST with Smoother and Scan-Chain Reorder", Proceedings of 13th IEEE Asian Test Symposium (ATS), pp. 40-45, November 2004.
  7. S. Z. Islam, M. A. M. Ali & Md. L. Ali, "Development of an LFSR based test pattern generator for functional logic testing", Proceeedings of 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 591-594, December 2003.
  8. Y. Shi and Z. Zhang, "Multiple Test Set Generation Method for LFSR-based BIST", Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 863-868, 2003.
  9. S. Bae, S. Yoon, S. Kim and S. Kang, "Test Pattern Generation Using a Dual MAC Unit", Journal of the Korean Physical Society, vol. 41, no. 6, pp. 974-981, December 2002.
  10. N.-C. Lai and S.-J. Wang, "Á Reseeding Technique for LFSR-Based BIST Applications", Proceedings of 11th IEEE Asian Test Symposium (ATS), pp. 206-211, Guam, November 18-20, 2002.
  11. M. A. M. Ali, S. Z. Islam & M. L. Ali, "Test processor chip design with complete simulation result including reseeding technique", Proceedings of IEEE International Conference on Semiconductor Electronics, pp. 218-221, December 2002.