Citations

  1. "The Future of Delta IDDQ Testing", B. Kruseman, R. van Veen and K. van Kaam, IEEE International Test Conference (ITC), pp. 101-110, 2001.
  2. "Built-In Current Sensor for ÄIDDQ Testing of Deep Submicron Digital CMOS ICs", J.R. Vazquez and J.P. de Gyvez, 22nd IEEE VLSI Test Symposium, pp. 53-58, 2004.
  3. "ÄIDDQ Testing of CMOS Data Converters", S. Yellampalli and A. Srivastava, Journal of Active and Passive Electronic Devices, vol. 4, no. 1-4, pp. 63-89, 2009.
  4. "Optimierung von Fehlererkennungsschaltungen auf der Grundlage von komplementaren Erganzungen fur 1-aus-3 und Berger Codes", Alexei Morozov, Universitat Potsdam, Institut fur Informatik, Ph.D. Thesis, March 2005.