Citations

    1. "A Totally Self -Checking Checker for Borden's Code" Niraj K. Jha, IEEE Trans. on CAD, VOL.8 No. &, July 1989 pp. 731-736.
    2. " Fault Detection in CVS Parity trees: Application to SSC CVS parity and two-rail checkers" N. K. Jha, Proc. IEEE Int. Test Conference, 1989, pp.407-414.
    3. "Strongly fault secure and Strongly Self-Checking Domino CMOS implementations of Totally Self-Checking Circuits", N. K. Jha, IEEE Transactions on Computer-Aided Design Vol. 9 No. 3, March 1990, pp. 332-336.
    4. "Reliable Floating-Point  Arithmetic  Algorithms for Error-Coded Operands", Jien-Chung Lo, IEEE Trans. on Computer, Bol. 43, No. 4, April 1994, pp. 400-412.
    5. "Simple binary to residue transformation with respect to 2m  +1 moduli.", F. Pourbigharaz and H. MM. Yassine, IEE Proc. -Circuits Devices Syst., Vol. 141, No. 6, December 1994, pp. 522-526.
    6. "Self Testing Checkers for Arithmetic Codes with Any Check Base A", J. S. Piestrak, Proc. 1991 Pacific Rim Int. Symp. Fault-Tolerant Syst. Kawasaki, Japan, Sept. 26-27, 1991, pp. 162-167.
    7. "Concurrent Error Detection and Correction in Real - Time Systolic Sorting Arrays", Sy-Yen Kuo and Sheng-Chiech Liang,  IEEE Trans. on Computers,. under review.
    8. "A CAD framework for efficient Self-Checking Data Path Design", R.O. Duarte, I. Alzaher nad M. Nicolaidis, Proc. of 3rd IEEE Int. On-Line Testing Workshop 1997, pp. 28-35.
    9. "On-Line Testing for VLSI - A Compendium of Approaches", M. Nicolaidis and Y. Zorian, Journal of Electronic Testing: Theory and Applications, Feb./April 1998, pp. 7-20.
    10. "Embedded Self-Testing Checkers for Low-Cost Arithmetic Codes", S. Tarnic and A. Stroele, Proc. of Int. Test Conference 1998, ITC-98.
    11. " A CAD Framework for Generating Self-Checking Multipliers Using Residue Arithmetic Codes", I. Alzaher Noufal and M. Nicolaidis, Proc. of 4th IEEE Int. On-Line Testing Workshop 1998, pp. 146-151.
    12. " On the Effectiveness of Residue Code Checking for Parallel Two's Complement Multipliers", U. Sparmann, and S. M. Reddy, Proc. of FTCS-24, June 15-17, 1994, pp.219-228.
    13. "A CAD Framework for Gemerating Self-Checking Multipliers Based on Residue Codes", I. A. Noufal, M. Nicolaidis, Proc of Design, Automation and Test in Europe, 1999, pp. 122-129.
    14. "Efficient Design of Totally Self Checking Checker-Decoders for All Cyclic AN Codes", A. Paschalis, D. Gizopoulos, M. Psarakis and M. Nicolaidis, 5th IEEE Int. On-Line Testing Workshop, 1999.
    15. D.3 '' On Fault Diagnosis and Cellular Realization of Some Error Detecting/Correcting Codes'', Gosta Pada Biswas, Ph.D. dissertation, Indian Institute of Technology, Kharagpur, 1997.
    16. D.4 "Cresterea fiabilitatii si disponibilitatii sistemelor de calcul prin eficientizarea autocontrolului", N. Petrakis, Universitate Tehnica Din Timisoara, Timisoara, 1995.
    17. B.2 Digital Systems Testing and Testable Design, M. Abramovici, M. A. Breuer and A. D. Friedman, Computer Science Press 1990
    18. B.3 Testing and Reliable Design of CMOS Circuits, Niraj K. Jha and Sandip Kundu, Kluwer Academic Publishers, 1990.
    19. "Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders," S.J. Piestrak, IEEE Transactions on Computers, vol. 43, no. 1, pp. 68-77, January, 1994.
    20.  "Fault localization, error correction, and graceful degradation in radix 2 signed digit-based adders", Cardarilli, G.C.   Ottavi, M.   Pontarelli, S.   Re, M.   Salsano, A., IEEE Transactions on Computers, May 2006 Volume: 55,  Issue: 5, pp. 534-540.
    21. "Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance", A. P. Kakaroudas, K. Papadomanolakis, V. Kokkinos  and C. E. Goutis,  Lecture Notes in Computer Science, Volume 1918/2000, pp. 187-194.
    22. "Fault tolerant design of signed digit based FIR filters", Cardarilli, G.C.   Pontarelli, S.   Re, M.   Salsano, A., Proceedings. 2006 IEEE International Symposium on Circuits and Systems, 2006. ISCAS 2006.
    23. "Efficient new approach for modulo 2n-1 addition in RNS", Patel, R.A.   Benaissa, M.   Boussakta, S. IEE Proceedings -Computers and Digital Techniques,  Nov. 2006
      Volume: 153,  Issue: 6, pp.399-405.
    24. "An On-Line Error-Detectable High-speed Array Divider", Naofumi Takagi and Shuzo Yajima , Systems and Computers i n Japan, Vol. 22, No. 1, 1991, Translated from Denshi Joho Tsushin Gakkai Ronbunshi, Vol. 73-DI, No. 2, February 1990, pp. 148-153.
    25. "Design of low-power on-line reconfigurable datapaths using self-checking circuits", Kakarountas, A.P.   Kokkinos, V.   Goutis, C.E. , The 8th IEEE Int. Conference on Electronics, Circuits and Systems, 2001. ICECS 2001.,  vol.3, pp. 1565-1568.
    26. "Embedded Borden 2-UED code checkers" Tarnick, S., 12th IEEE International On-Line Testing Symposium, 2006. IOLTS 2006.
    27. "A low power fault secure timer implementation based on the Gray encoding scheme", Papadomanolakis, K.S.   Kakarountas, A.P.   Sklavos, N.   Goutis, C.E. 9th International Conference on Electronics, Circuits and Systems, 2002, On page(s): 537- 540 vol.2
    28. "Oscillation control in logic simulation using dynamic dominance graphs", Peter Dahlgren, Design Automation Conference 1996, pp. 155 - 160. 
    29. "Optimization of Self Checking FIR filters by means of Fault Injection Analysis", Pontarelli, S.   Sterpone, L.   Cardarilli, G.C.   Re, M.   Reorda, M.S.   Salsano, A.   Violante, M., DFT '07. 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, 2007.26-28 Sept. 2007,  On page(s): 96-104.
    30. "Self-Testing Embedded Borden t-UED Code Checkers for t=q2^k-1 with q=2^m-1",  S. Tarnick, Journal of Electronic Testing, Volume 24, Number 6 / December, 2008, pp. 509-527.