Citations

  1. "A Totally Self -Checking Checker for Borden's Code" Niraj K. Jha, IEEE Trans. on CAD, VOL.8 No. &, July 1989 pp. 731-736.
  2. " Fault Detection in CVS Parity trees: Application to SSC CVS parity and two-rail checkers" N. K. Jha, Proc. IEEE Int. Test Conference, 1989, pp.407-414.
  3. "Strongly fault secure and Strongly Self-Checking Domino CMOS implementations of Totally Self-Checking Circuits", N. K. Jha, IEEE Transactions on Computer-Aided Design Vol. 9 No. 3, March 1990, pp. 332-336.
  4. "Efficient design of CMOS TSC checkers", S. Manjunanh & D. Radhakrtshuan, Int J. of Electronics, 1991, Vol. 71, No. 1, pp. 67-79.
  5. "A Novel Area-Time Efficient Static CMOS Totally Self -Checking Comparator", J.  C. Lo, IEEE Journal of Solid-State Circuits, Vol. 28, NO. 2, February 1993, pp.165-168.
  6. "Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning", T. R. N. Rao, G. L. Feng, M. S. Kolluru and Jien - Chung Lo,  IEEE Trans. on Computers, Vol. 42, No. 8, August 1993, 1020-1024.
  7. "Fault Secure Property Versus Strongly Code Disjoint Checkers.", M. Nicolaidis, IEEE Trans. on Comp. Aided Design, 13(5): 651-658, 1994.
  8. "Efficient Structured Design of Robustly Testable CMOS TSC M-out-of-2M Code Checkers", Th. Haniotakis and A. Paschalis, Proc.of 1st IEEE International On-Line Testing Workshop, Nice, France, July 4-6, 1995, pp. 233-237.
  9. "Concurrent Error Detection of CMOS Digital and Analog Faults", Y. R. Shien and C. W. Wu, Proc. of European Test Conference (ETC93), Rotterdam, The Netherlands, April 19-22, 1993, pp. 74-81.
  10. "Area-Efficient Totally Self-Checking Checkers for m-out-of-n code", Wen-Feng Chang and Cheng-Wen Wu, IEEE Trans. on Computers, under review.
  11. " Modular Design of Self - Testing Checkers For m-out-of-n Codes", S. J. Piestrak, Proc. 2nd IEEE Intern. On-Line Testing Workshop, Biarritz, France July 1996, pp. 132-135.
  12. "Testable Designs of One-Count Generators", T. Haniotakis, A. Paschalis, C. Halatsis and G. Philokyprou, Int. Journal of Electronics, 1998, Iss. 5, pp. 629-650.
  13. "On-Line Testing for VLSI - A Compendium of Approaches", M. Nicolaidis and Y. Zorian, Journal of Electronic Testing: Theory and Applications, Feb./April 1998, pp. 7-20.
  14. "On-Line Testing for VLSI: state of the art and trends", M. Nicolaidis, Integration, The VLSI Journal, Dec. 1998, pp. 197-210.
  15. "Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters, S. Piestrak, Journal of Electronic Testing: Theory and Applications, Feb./April 1998, pp. 63-68.
  16. "General Design Procedure of Self-Testing Checkers for All m-out-of-n Codes with m³3 Using Parallel Counters, S. Piestrak, Proc. of 4th IEEE Int. On-Line Testing Workshop 1998, pp.182-186.
  17. "Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Codes", 17th IEEE VLSI Test Symposium, Dana Point , California, April 25-29, 1999, pp. 361-369.
  18. "Efficient Design of Totally Self Checking Checker-Decoders for All Cyclic AN Codes", A. Paschalis, D. Gizopoulos, M. Psarakis and M. Nicolaidis, 5th IEEE Int. On-Line Testing Workshop, 1999.
  19. "An efficient TSC 1-out-of-3 code checker", Paschalis, A.M.   Efstathiou, C.   Halatsis, C., IEEE Transactions on Computers, Vol.: 39, Issue: 3, Mar 1990, pp. 407-411.
  20. "A methodology for the design of SFS/SCD circuits for a class of unordered codes Source", Sandeep Pagey, S. D. Sherlekar, G. Venkatesh, Journal of Electronic Testing: Theory and Applications Volume 2 ,  Issue 3  (August 1991) pp. 261 - 277.  
  21. "Low-Cost Modular Totally Self-Checking Checker Design for m-out-of-n Code", Wen-Feng Chang, Cheng-Wen Wu, IEEE Transactions on Computers, vol. 48, no. 8, August, 1999, pp. 815-826.
  22. "Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning'," Stanislaw J. Piestrak, IEEE Transactions on Computers, vol. 51, no. 6, pp. 735-736, June, 2002.
  23. "Designing FPGA based self-testing checkers for m-out-of-n codes", Matrosova, A.   Ostrovsky, V.   Levin, I.   Nikitin, K., 9th IEEE On-Line Testing Symposium, 2003, IOLTS 2003, 7-9 July 2003, pp.49- 53.
  24. "Cellular realization of TSC checkers for error detecting codes", Pal, A., IEEE Region 10 Conference on Computer and Communication Systems 1990, TENCON 90, Hong Kong, 24-27 Sep. 1990, pp.687-691 vol.2.
  25. "Design of Self-Checking Processors Using Efficient Berger Check Prediction Logic", T. R. N. Rao, Gui-Liang Feng and Mahadev S. Kolluru, in Book Foundations of Dependable Computing,System Implementation edited by Gary M. Koob and Clifford G. Lau, Springer,Volume 285, August 19, 2007, pp.35-68.
  26. "Universal TSC module and its application to the design of TSC circuits",  S. Pagey and A. J. Al-Khalili, Microelectronics Journal, Volume 28, Issue 1, January 1997, Pages 29-39.
  27. "On the design of self-checking controllers with datapath interactions" Oikonomakos, P., Zwolinski, M. IEEE Transactions on Computers 55 (11), 2006, pp. 1423-1434.
  28. "Design of embedded m-out-of-w code checkers using complete parallel counters", Tarnick, S. Proc., 13th IEEE International On-Line Testing Symposium 2007, IOLTS 2007, pp. 285-292.
  29. Residue-to-mixed radix converter with totally self-checking code error detection Mathew, J., Radhakrishnan, D. International Symposium on IC Technology, Systems and Applications 1999, pp. 483-485.
  30. "Concurrent checking for VLSI", Nicolaidis, M., Anghel, L. 1999 Microelectronic Engineering 49 (1), pp. 139-156.
  31. "TSC Berger-code checker design for 2r-1-bit information", Chang, W.-F., Wu, C.-W. 1999 Journal of Information Science and Engineering 15 (3), pp. 429-441.
  32. Design of CMOS PSCD circuits and checkers for stuck-at and stuck-on faults Shieh, Y.-R., Wu, C.-W. 1998 VLSI Design 5 (4), pp. 357-372.
  33. "Optimierung von Fehlererkennungsschaltungen auf der Grundlage von komplementaren Erganzungen fur 1-aus-3 und Berger Codes", Alexei Morozov, Universitat Potsdam, Institut fur Informatik, Ph.D. Thesis, March 2005.
  34. 34. '' On Fault Diagnosis and Cellular Realization of Some Error Detecting/Correcting Codes'', Gosta Pada Biswas, Ph.D. dissertation, Indian Institute of Technology, Kharagpur, 1997.
  35. "Cresterea fiabilitatii si disponibilitatii sistemelor de calcul prin eficientizarea autocontrolului", N. Petrakis, Universitate Tehnica Din Timisoara, Timisoara, 1995.
  36. Error-Control Coding for Computer Systems, T.R.N. Rao and E. Fujiwara, Prentice-Hall International Editions, 1989.
  37. Testing and Reliable Design of CMOS Circuits, Niraj K. Jha and Sandip Kundu, Kluwer Academic Publishers, 1990.
  38. Design of self-testing checkers for unidirectional error detecting codes, Stanislaw J. Piestrak, Wroclaw, 1995.