Citations

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    8. Ghassem Jaberipur , "A One-Step Modulo 2n+1 Adder Based on Double-LSB Representation of Residues", The CSI Journal on Computer Science and Engineering Vol. 4, No. 2&4, 2006, pp. 10-16
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    11. Jian Zhang, Shuguo Li, "High Speed Parallel Architecture for Cyclic Convolution Based on FNT," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), May 13-15, 2009, Tampa, Florida, USA, pp.199-204.
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    14. On the modulo 2n+1 multiplication for diminished-1 operands, C. Efstathiou, I. Voyiatzis and N. Sklavos, 2008 International Conference on Signals, Circuits and Systems, November 7-9, Hammamet, Tunisia, pp. 1-5.
    15. Design and Implementation of Area-Efficient Weighted Modulo 2n+1 Multipliers, T.-B. Juang, K.-L. Wu and C.-C. Chiu, Proc. of the Taiwanese Symposium on System Prototyping, Circuit Design and Innovation, Taipei, Taiwan, October 10-16, 2009, pp. 376-381.