Citations

1. "Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model", M. Psarakis, D. Gizopoulos, A. Paschalis and Y. Zorian, 16th IEEE VLSI Test Symposium, 1998, pp. 152-157.
2. "Sequential fault modeling and test pattern generation for CMOS iterative logic arrays", Psarakis, M., Gizopoulos, D., Paschalis, A., Zorian, Y.,IEEE Transactions on Computers. Vol. 49, no. 10, pp. 1083-1099. Oct. 2000
3. "Built-in sequential fault self-testing of array multipliers", Psarakis, M.   Gizopoulos, D.   Paschalis, A.,    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, March 2005, Volume: 24,  Issue: 3, pp. 449- 460.
4. "An effective BIST architecture for sequential fault testing in array multipliers"
   Psarakis, M.   Gizopoulos, D.   Paschalis, A.   Zorian, Y., Proceedings. 17th IEEE VLSI Test Symposium, 1999, San Diego, California, pp. 252-258.
5. "Efficient built-in self-test techniques for sequential fault testing of iterative logic arrays Source",  Shyue-Kung Lu, Mao-Yang Dong Proceedings of the 6th WSEAS International Conference on Applied Informatics and Communications, 2006, Elounda, Greece, pp. 513-517.