Citations

1. A. Dutta, M. Shah, G. Swathi and R. Parekhji, "Design Techniques and Tradeoffs in Implementing Non-Destructive Field Test Using Logic BIST Self-Test", Proc. of 15th IEEE Int. On-Line Testing Symposium (IOLTS), pp. 237-242, June 2009. 
2. S. Manich, L. Garcia-Deiros and J. Figueras, "Minimizing Test Time in Arithmetic Test-Pattern Generators with Constrained Memory Resources", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 11, pp. 2046-2058, November 2007.
3. J. Solana, "A Deterministic BIST Scheme for Test Time Reduction in VLSI Circuits", VLSI Circuits and Systems II (eds. J. Lopez, Fr. Fernandez, J. Lopez-Villegas, J. de la Rosa), Proceedings of SPIE, vol. 5837, pp. 1086-1097, June 2005.
4. S. Manich, L. Garcia, L. Balado, E. Lupon, J. Rius, R. Rodriguez & J. Figueras, "BIST technique by equally spaced test vector sequences", Proceedings of 22nd IEEE VLSI Test Symposium (VTS), pp. 206-211, April 2004.
5. S. Manich, L. Garcia, L. Balado, E. Lupon, J. Rius, R. Rodriguez and J. Figueras, "On the Selection of Efficient Arithmetic Additive Test Pattern Generators", Proceedings of European Test Workshop (ETW), pp. 9-14, 2003.