Citations

1. "Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes," S.J. Piestrak, IEEE Transactions on Computers, vol. 51, no. 2, pp. 229-234, February, 2002.
2. "Low Cost and High Speed Embedded Two-Rail Code Checker," Martin Oma, Daniele Rossi, Cecilia Metra, IEEE Transactions on Computers, vol. 54, no. 2, pp. 153-164, February, 2005.
3. "A Current Mode, Parallel, Two-Rail Code Checker", Matakias, S.   Tsiatouhas, Y.   Haniotakis, T.   Arapoyanni, A.   IEEE Transactions on Computers, Aug. 2008, Vol. 57,  Issue: 8,  pp. 1032-1045.
4.  "Dependable design technique for system-on-chip", Pavel Kubalik and Hana Kubatova, Journal of Systems Architecture, Volume 54, Issues 3-4, March-April 2008, pp.452-464.