Citations

1. "Minimal C-Testable Tests for Block-CLA Adders", MR. Moor, Int. Journal of Electronics, 1998, Iss. 5, pp. 611-628.
2. "Design of C-Testable Multipliers Based on the Modified Booth Algorithm," Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu, Asian Test Symposium, pp. 42, Sixth Asian Test Symposium (ATS'97), 1997.
3. "A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier," S. M. Aziz, C. N. Basheer, J. Kamruzzaman, IEEE International Workshop on Electronic Design, Test and Applications, , (DELTA '02), 2002, Christchurch, New Zealand, January 29-31, pp. 504.
4. "Test Generation for Transition Delay and RS-CFM Faults in Modified Booth Multipliers", Hsing-Chung Liang and Pao-Hsin Huang, The 18th VLSI design/Symposium, 2007.
5. Testing transition delay faults in modified Booth multipliers by using C-testable and SIC patterns", Hsing-Chung Liang   Pao-Hsin Huang, Chung Yung Christian Univ., Chung Yung,, Oct. 30 -Nov. 2 2007, pp. 1-4
6. "Accumulator-based pseudo-exhaustive two-pattern generation",  I.  Voyiatzis, Journal of Systems Architecture, Volume 53, Issue 11, November 2007, Pages 846-860
7. "Level-testability of multi-operand adders", N. Kito and N. Takagi, ATS 2008.
8. "Testing Transition Delay Faults in Modified Booth Multipliers", Hsing-Chung Liang, Pao-Hsin Huang, Yan-Fei Tang, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Sept. 2008, Volume: 27,  Issue: 9
   pp. 1693-1697.
9. "Testing and Diagnostics of SIMD Arrays," J. Sosnowski, EUROMICRO Conference, pp. 96, 23rd EUROMICRO Conference '97 New Frontiers of Information Technology, 1997.