Citations
- Eric Quinnel, "Floating-point fused multiply-add architectures", PhD Thesis, University of Texas - Austin.
- Shen Sun and Carl Sechen, "Post-Layout Comparison of High Performance 64b Adders in Energy-Delay Space", in Proceedings of International Conference on Computer Design 2007 (ICCD 07).
- Eric Quinnel, Earl E. Swartzlander and Carl Lemonds, "A Three-Path Floating-Point Fused Multiply-Add Design"
- Y. Choi and E. E. Swartzlander, "Speculative Carry Generation with Prefix Adder", in IEEE Transactions on VLSI Systems, March 2008
- S. Das and S. P. Khatri, "A Novel Hybrid Parallel-Prefix Adder Architeture with Efficient Timing-Area Characteristic", IEEE Transactions on VLSI Systems, March 2008.
- Yi Zhu, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, "Timing-Power Optimization for Mixed Radix Ling Adders by Integer Linear Programming", in Asia and South Pacific Design Automation Conference 2008.
- J. H. Park, H. K. Dai, "Reconfigurable hardware solution to parallel-prefix computation", Journal of Supercomputing, Springer - Netherlands, May 2007.
- X. Y. Yu, R. Montoye, K. Nowka, B. Zeydel, V. Oklobdzija, "Circuit Design Style for Energy Efficiency: LSDL and Compound Domino", International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sept. 2006
- Johannes Grad, James Stine, "Low Power Binary Addition Using Carry Increment Adders" in Proc. of the IEEE International Symposium on Circuit and Systems, May 2006.
- Jean-Louis Roch, Daouda Traore, "Un algorithme adaptatif optimal pour le calcul parallele des prefixes" Colloque Africain sur la Recherche en Informatique, CARI'2006. Nov 2006.
- Johannes Grad, "Analysis and Implemenentation of Binary Addition in Nanometer CMOS technology", PhD Thesis, Illinois Institute of Technology, April 2005.
- Jean-Louis Roch, Daouda Traore, Julien Bernard, "On-line adaptive parallel prefix computation", in Proceedings of Europar, Sept. 2006.
- Dong-Yu Zheng, Yan Sun, Shao-Qing Li, and Liang Fang, "A 485ps 64-Bit Parallel Adder in 0.18ėm CMOS", Journal of Computer Science and Technology, pp.25-27, Jan. 2007.
- Su Kang and Wang Chenghua, "DSP System for Digital Storage Oscilloscope", Journal Of Nanjing University Of Aeronautics and Astronautics, 2006, Vol.38, No.6, pp.769-774.
- Kostas Vitoroulis, Asim J. Al-Khalili "Parallel prefix adders", Lecture Presentation at Digital Design and Synthesis Course, Electrical and Computer Engineering department, University of Concordia, Canada, 2006.
- Beerel, Peter A., Chugg Keith M., Dimou Georgios D., Thiennviboon Phunsak, "Reduced-latency soft-in/soft-out module", United States Patent 7197691.
- Jong-Suk Lee and Dong Sam Ha, "High Speed 1-bit Bypass Adder Design for Low Precision Additions", in Proceedings of International Symposium on Circuits and Systems (ISCAS), 2007.
- Vazquez and Elisardo Antelo, "New Insights on Ling Adders", Technical Report, Dept. Electronic and Computer Engineering. University of Santiago de Compostela, 2007.
- Yi Zhu, Jianhua Liu, Haikun Zhu and Chung-Kuan Cheng, "Optimizing Mixed-Radix Ling Adders using Integer Linear Programming", in Proceedings of ACM Intenational Workshop on Logic Synthesis (IWLS), 2007.
- Yen-Chun Lin, Li-Ling Hung, "Four families of computation-efficient parallel prefix algorithms for multicomputers", Technical report NTUST-CSIE-08-01, National Taiwan University of Science and Technology, Feb 2008.
- Chen, S. Wei, S, "A fast algorithm for RNS-to-binary conversion", in WSEAS Transactions on Computers, vol. 6, no. 5, May 2007, pp. 733-740 .
- Vitoroulis, K., Obuchowicz, T., Al-Khalili, A.J. "A CAD tool for the automatic generation of synthesizable parallel prefix adders in VHDL", in Proceedings of SPIE - The International Society for Optical Engineering 6798.
- Vitoroulis, Konstantinos; Al-Khalili, Asim J., "Performance of Parallel Prefix Adders implemented with FPGA technology,"in proceedings of IEEE Northeast Workshop on Circuits and Systems (NEWCAS) pp.498-501, 5-8 Aug. 2007.
- Matsunaga Taeko, Kimura Shinji, Matsunage Yusuke, "Synthesis of parallel prefix adders based on Ling's carry computation", Technical report of IEICE. VLD, Vol.107, No.336, pp. 49-54.
- Voyiatzis I., C. Efstathiou, "An Efficient architecture for accumulator-based test generation of SIC pairs", in proceedings of IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, March 2008.
- H. T. Vergos, C. Efstathiou, "Efficient modulo 2n+1 adder architectures", Integration, the VLSI Journal, 2008.
- Yen-Chun Lin, Li-Ling Hung, "Parallel-prefix algorithms on the multi-computer", WSEAS Transactions on Computer Research, 2008.
- Vazquez and Elisardo Antelo, "New Insights on Ling Adders", in proceeding of IEEE International Conference on Application-Specific, Systems, Architectures and Processors (ASAP), 2008.
- Xiao Jiusi and Zhang Lei, "Verification of the Design of High-Speed Parallel prefix Ling adders based on Verilog HDL", Computer and Digital Engineering, 2008, vol. 36, no. 5, pp.150-152.
- Hua-yi Hong, "Implementation of Variable-Latency Floating-Point Multipliers for Low-Power Applications", Master of Engineering, National Sun Yat-Sen University, Taiwan, Jul. 2008.
- S. Das and S. Khati, "A timing-driven synthesis approach of a fast four-stage hybrid adder in Sum-of-Products", IEEE Midwest Symposium on Circuits and Systems, Aug. 2008, pp. 507-510.
- "The High-Speed Segment Adders in Parallel Computation", Rong-Jong Fan, MSc Thesis, TsingHua University, China
- "Fast problem-size-independent parallel prefix circuits", Yen-Chun Lin, Li-Ling Hung, Journal of Parallel and Distributed Computing, Elsevier
- Algorithmes paralleles auto-adaptatifs et applications, Daouda Traore, PhD Thesis, DOCTEUR DE L'Institut Polytechnique de Grenoble
- Chung-Kuan Cheng, "Design Space Exploration for Power Efficient Mixed-Radix Ling adders", IEEE Symposium Computer Arithmetic 2009
- Vasquez Alvarez Alvaro, "High-Performance Decimal Floating Point Units", PhD Dissertation - University Santiago de Compostela, Spain, 2009
- "Implement of high speed DDS circuit design using improved CORDIC algorithm" Yao, Y., Fu, D., Yang, X. Huazhong Keji Daxue Xuebao (Ziran Kexue Ban)/Journal of Huazhong University of Science and Technology (Natural Science Edition) Volume 37, Issue 2, February 2009, Pages 25-27+56
- Jun-yu Ke, "Improved Parallel Prefix on the Multicomputer", Master Thesis, Department of Computer Science and Information Engineering, National Taiwan University of Science and Technology, Taiwan
- J. Chen and J. E. Stine, "Parallel prefix Ling structures for modulo 2n-1 addition", in Application-specific systems, architectures and processors, ASAP 2009.
- I. Voyiatzis, C. Efstathiou, "An efficient architecture for accumulator-based test generation of SIC pairs", Elsevier, Microelectronics Journal 2009.
- Jong-Suk Lee and Dong Sam Ha, "FleXilicon Architecture and Its VLSI Implementation", IEEE Transactions on VLSI Systems 2009.
- Implementation of a speculative Ling adder Mehta, M., Kumar Nuggehalli Ramachandra, A., Swartzlander Jr., E.E. Proc. of SPIE The International Society for Optical Engineering, Vol. 7444, 2009, Article number 74440K
- A Novel Logarithmic Prefix Adder with minimized power delay product, P. Ramanathan, P. T. Vanathi, Journal of Scientific and Industrial Research, vol. 69, Jan 2010, pp. 17-20.
- Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product P.Ramanathan1 and.P.T.Vanathi, International Journal on Electronics, Circuits, and Systems, 2009, World Academy of Science Engineering and Technology.