Citations

  1. Σχεδίαση Αυτοελεγχόμενων Ελεγκτών σε Τεχνολογία VLSI, X. Καβουσιανός, Διδακτορική Διατριβή, Τμήμα Μηχανικών Η/Υ και Πληροφορικής, Πανεπιστήμιο Πατρών, Σεπτέμβριος 2000.
  2. A Code Placement Technique for Improving the Performance Yield of Processors with Defective Caches, T. Ishihara and F. Fallah, IEICE Technical Reports, Vol. 105, No. 350, 2005, pp. 61-66.
  3. A Cache-Defect-Aware Code Placement Algorithm for Improving the Performance of Processors, T. Ishihara and F. Fallah, IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2005), San Jose, CA, USA, November 6-10, 2005, pp. 995-1001.
  4. Customizable Fault Tolerant Caches for Embedded Processors, S. Ramaswamy and S. Yalamanchili, 24th IEEE International Conference on Computer Design (ICCD 2006), October 1-4, 2006, Jan Jose, California, USA, pp. 108-113.
  5. Limits on Voltage Scaling for Caches Utilizing Fault Tolerant Techniques, M. A. Makhzan, A. Khajeh, A. Eltawil and F. Kurdahi, IEEE International Conference on Computer Design (ICCD 2007), October 7-10, 2007, Lake Tahoe, California, USA, pp. 488-495.
  6. A Code Placement Technique for Improving the Performance of Processors with Defective Caches, T. Ishihara and F. Fallah, 14th International Workshop on Logic and Synthesis (IWLS 2005), June 8-10, 2005, Lake Arrowhead, California, USA, pp. 210-214.
  7. A Code Placement Technique for Improving the Performance Yield of Processors with Defective Caches, F. Fallah and T. Ishihara, Kyoshu University Institutional Repository, Technical Report No. 102, 2005, pp. 179-184.