Citations

1. "Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources", Manich, S.   Garcia-Deiros, L.   Figueras, J., IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Nov. 2007, Vol. 26, Issue: 11, pp. 2046-2058.
2. "A low-cost BIST scheme for test vector embedding in accumulator-generated sequences", Ioannis Voyiatzis, VLSI Design, Vol. 2008 ,  Issue 2  (January 2008) pages: 8
3. "A Low-Cost Accumulator-Based Test Pattern Generation Architecture", Magos, D.   Voyiatzis, I.   Tarnick, S., 14th IEEE International On-Line Testing Symposium, 2008. IOLTS '08,7-9 July 2008, pp. 267-272.
4. "Embedding Test Patterns in Accumulator-Generated Sequences in O(1) Time," Nestor Ioannidis, Ioannis Voyiatzis, Informatics, Panhellenic Conference on, pp. 55-59, 2009 13th Panhellenic Conference on Informatics, 2009.