Citations

      1. Modified Modulo 2n±1 RNS Multipliers, C. - F. Ku, Master of Science Thesis, Industrial Technology R&D Master Program on IC Design (RDIC), National Tsing Hua University, Taiwan, R.O.C, February 2007.
      2. A Low Cost Modulo 2n±1 RNS Multiplier, Yu-Po Yang, Master of Science Thesis, Industrial Technology R&D Master Program on IC Design (RDIC), National Tsing Hua University, Taiwan, R.O.C, July 2007.
      3. Small Area Modulo 2n±1 RNS Multipliers, Chien-Min Chen, Master of Science Thesis, Industrial Technology R&D Master Program on IC Design (RDIC), National Tsing Hua University, Taiwan, R.O.C, July 2007.
      4. Κυκλώματα Ύψωσης στο Τετράγωνο για το Σύστημα Αριθμητικής Υπολοίπων, Αν. Σπύρου, Μεταπτυχιακή Διπλωματική εργασία, Τμήμα Μηχανικών Η/Υ & Πληροφορικής, Πανεπιστήμιο Πατρών, Μάϊος 2009.
      5. Architecture Optimization of Word-length Booth Multiplier, Y-J Zhu and Y. Xi, Journal of Fudan University (Natural Science), Vol. 44, No. 1, 2005, pp. 85-89.
      6. New Booth Modulo m Multipliers with Signed-Digit Number Arithmetic, S. Chen and S. Wei, Information Processing Society of Japan Journal, Vol. 46, No. 12, December 2005, pp. 3030-3039.
      7. New Booth Modulo m Multipliers with Signed-Digit Number Arithmetic, S. Chen and S. Wei, Information and Media Technologies, Vol. 1, No. 1, 2006, pp. 212-221 .
      8. Performance Evaluation of Signed-Digit Architecture for Weighted-to-Residue and Residue-to-Weighted Number Converters with Moduli Set (2n-1, 2n, 2n+1), S. Chen and S. Wei, Information Processing Society of Japan Journal, Vol. 47, No. 6, June 2006, pp. 328-337.
      9. Performance Evaluation of Signed-Digit Architecture for Weighted-to-Residue and Residue-to-Weighted Number Converters with Moduli Set (2n-1, 2n, 2n+1), S. Chen and S. Wei, Information and Media Technologies Vol. 1, No. 2, 2006, pp. 899-908.
      10. Modified Overlap Technique using Fermat and Mersenne Transforms, R. Conway, IEEE Transactions on Circuits and Systems II, Vol. 53, No.8, August 2006, pp. 632-636.
      11. Design of an 8-bit Multiplier Accumulator Embedded in MCU, H. Guize, H. Yueli and X. Huifang, Computer Measurement and Control, Vol.14, No. 5, May 2006, pp.651-654.
      12. Efficient New Approach for Modulo 2n-1 Addition in RNS, R. A. Patel, M. Benaissa and S. Boussakta, IEE Proceedings, Computers and Digital Techniques, Vol. 153, No. 6, November 2006, pp. 399-405.
      13. Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero, R. A. Patel, M. Benaissa and S. Boussakta, IEEE Transactions on Computers, Vol. 56, No. 11, November 2007, pp. 1484-1492.
      14. Unified Dual-Field Multiplier in GF(P) and GF(2k), C. W. Chiou, C.-Y. Lee and J. M. Lin, IET Information Security, Vol. 3, No. 2, June 2009, pp. 45-52.
      15. A Low-Complexity High-Radix RNS Multiplier, I. Kouretas and V. Paliouras, IEEE Transactions on Circuits and Systems I, to appear.
      16. Booth Memoryless Modular Multiplier with Signed-Digit Number Representation, S. Chen, S. Wei and K. Shimizu, IEEE Asia-Pacific Conference on Circuits and Systems, December 6-9, 2004, Tainan, Taiwan, pp. 21-24.
      17. Number Conversions between RNS and Mixed-Radix Number System based on Modulo (2p-1) Signed-Digit Arithmetic, S. Wei, 18th Symposium on Integrated Circuits and System Design, Florianolpolis, Brazil, Septemeber 4-8, 2005, pp. 160-165.
      18. A Simplified Modulo 2n-1 Squaring Scheme for Residue Number System, A. Hariri, K. Navi, R. Rastegar, International Conference on "Computer as a Tool" (EUROCON 2005), Belgrade, Serbia and Montenegro, November 21-24, 2005, pp. 615-618.
      19. A Multiplicative Inverse Algorithm Based on Modulo (2p-1) Signed-Digit Arithmetic for Residue to Weighted Number Conversion, S. Wei, IEEE International Symposium on Integrated Circuits (ISIC '07), September 26-28, 2007, Singapore, pp. 1-4.
      20. An Efficient Architecture of RNS based Wallace Tree Multiplier for DSP Applications, P. P. Kundu, O. Bandyopadhyay and A. Sinha, 51st IEEE Midwest Symposium on Circuits and Systems, (MWCAS 2008), August 10-13, 2008, Knoxville, Tennessee, USA, pp. 221-224.
      21. Design of Cost-Efficient Multipliers Modulo 2a-1, S. Piestrak, 2010 International Symposium on Circuits and Systems (ISCAS-2010), May 30 - June 2, 2010, to appear