Citations

1. Abu-Issa and S. Quigley, "Bit-Swapping LFSR and Scan-Chain Ordering: A Novel Technique for Peak- and Average-Power Reduction in Scan-Based BIST", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 5, pp. 755-759, May 2009.
2. K. Paramasivam, K. Gunavathi and A. Nirmalkumar, "Modified Scan Architecture for an Effective Scan Testing", Proc. of IEEE Region 10 Conference TENCON, pp. 1-6, November 2008.
3. L.-J. Lee, W.-D. Tseng and R.-B. Lin, "Power Reduction during Scan Testing Based on Multiple Capture Technique", IEICE Transactions on Electronics, vol. E91-C, no. 5, pp. 798-805, May 2008.
4. Abu-Issa and S. Quigley, "LT-PRPG: Power Minimization Technique for Test-per-Scan BIST", Proc. of 3rd Int. Conference on Design and Technology of Integrated Systems in Nanoscale Era, pp. 1-5, March 2008.
5. H.-Y Lin, W.-D. Tseng and L.-C. Lai, "Reduction of Test Power during Test Application in Full-Scan Sequential Circuits with Multiple Capture Techniques", Proc. of Int. Computer Symposium, pp. 254-259, Taipei, Taiwan, December 2006.