Citations

1. D. Mitra, S. Sur-Kolay and B.B. Bhattacharya, "Droop Sensitivity of Stuck-At Fault Tests", IET Computers & Digital Techniques, vol. 3, no. 2, pp. 175-183, March 2009.
2. J. Skarvada, T. Herrman and Z. Kotasek, "RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Design Tool", Proc. of 8th IEEE Workshop on RTL and High Level Testing, pp. 175-181, 2007.
3. J. Skarvada, "RT Level Test Optimization for Low Power Consumption", 3rd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, pp. 185-192, October 2007.
4. Ching-Cheng Lin, "Multiple Input Blocking Pattern Generator for Reducing Power Consumption during Scan Testing", Thesis, Department of Computer Science and Engineering, 2006.
5. M. Cho and D. Pan, "PEAKASO: Peak-Temperature Aware Scan-Vector Optimization", Proceedings of VLSI Test Symposium (VTS), pp. 52-57, April 2006.
6. "Low-Transition Test Pattern Generation for BIST-Based Applications", Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed, IEEE Transactions on Computers, vol. 57, no. 3, March 2008, pp. 303-315