Citations

    1. Contribution to the Study of the Common FFT Operator in Software Radio Context: Application to Channel Coding, A. Al Ghouwayel, Ph.D. Thesis, Universite de Rennes I, Institut d' electronique et de telecommunications de Rennes, Mention : Traitement du Signal et Telecommunications, January 2009.
    2. Two Modulo 2n±1 Adders, Ho-Chia Tseng, Master of Science Thesis, Industrial Technology R&D Master Program on IC Design (RDIC), National Tsing Hua University, Taiwan, R.O.C, October 2009.
    3. Power-Delay-Area Efficient Modulo 2n+1 Adder Architecture for RNS, R. A. Patel, M. Benaissa, S. Boussakta and N. Powell, Electronics Letters, Vol. 41, No. 5, March 2005, pp. 231-232.
    4. Efficient New Approach for Modulo 2n-1 Addition in RNS, R. A. Patel, M. Benaissa and S. Boussakta, IEE Proceedings, Computers and Digital Techniques, Vol. 153, No. 6, November 2006, pp. 399-405.
    5. A One-Step Modulo 2n+1 Adder Based on Double-lsb Representation of Residues, G. Jaberipur, The CSI Journal on Computer Science and Engineering, Vol. 4, No. 2 & 4, 2006, pp. 10-16.
    6. Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero, R. A. Patel, M. Benaissa and S. Boussakta, IEEE Transactions on Computers, Vol. 56, No. 11, November 2007, pp. 1484-1492.
    7. Area-Time Efficient Modulo 2n-1 Adder Design Using Hybrid Carry Selection, S.-H. Lin and M.-H. Sheu, IEICE Transactions on Information and Systems, Vol. E-91-D, No. 2, February 2008, pp. 361-362.
    8. VLSI Design of Diminished-One Modulo 2n+1 Adder Using Circular Carry Selection, S.-H. Lin and M.-H. Sheu, IEEE Transactions on Circuits and Systems-II, Vol. 55, No. 9, September 2008, pp. 897-901.
    9. Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication, I. Kouretas and V. Paliouras, 18th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation (PATMOS 2008), September 10-12, Lisbon, Portugal, Lecture Notes In Computer Science, Vol. 5349, L. Svensson and J. Monteiro (Eds.), Springer-Verlag, Heidelberg 2009, pp. 93-102.
    10. Bipartite Implementation of the Residue Logarithmic Number System, M. G. Arnold and J. Ruan, International Symposium on Optical Science and Technology, Conference 5910-Computer Arithmetic I, SPIE Annual Meeting, August 3, 2005, San Diego, California, pp. 1-9.
    11. Novel VLSI Design of Circular-Carry-Select (CCS) Based Diminished-One Modulo 2n+1 Adder, S.-H. Lin, M.-H. Sheu, K.-H. Wang, J.-J. Zhu and S.-Y. Chen, 18th VLSI Design / CAD Symposium, August 8-10, 2007, Hualian, Taiwan, pp. 13-16.
    12. New Circular-Carry-Select (CCS) Architecture for Diminished-One Modulo 2n+1 Addition, S.-H. Lin, M.-H. Sheu, Z.-M. Chen, 2007 IEEE Region 10 Conference (TENCON 2007), October 30-November 2, 2007, Taipei, Taiwan, pp. 1-4.
    13. Low-Power Logarithmic Number System Addition / Subtraction and their Impact on Digital Filters, I. Kouretas, Ch. Basetas and V. Paliouras, IEEE International Symposium on Circuits and Systems (ISCAS 2008), May 18 - 21, 2008, Seattle, Washington, USA, pp. 692-695.
    14. Modular Multipliers Using a Modified Residue Addition Algorithm with Signed-Digit Number Representation, S. Wei, International Multiconference of Engineers and Computer Scientists (IMECS 2009), March 18-20, 2009, Hong Kong, Vol. I, pp. 494-499.
    15. High-Radix Residue Arithmetic Bases for Low-Power DSP Systems, I. Kouretas and V. Paliouras, 16th International Conference on Digital Signal Processing (DSP 2009), Santorini, Greece, July 5-7, 2009.
    16. Efficient VLSI Design of Modulo 2n-1 Adder using Hybrid Carry Selection, S.-H. Lin, M.-H. Sheu, K.-H. Wang, J.-L. Zhu and S.-Y. Chen, IEEE Workshop on Signal Processing Systems, Shanghai, China, October 17-19, 2007, pp. 142-145.
    17. A New Residue Adder with Redundant Binary Number Representation, S. Wei, Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA), Toulouse, France, June 28-July 1, 2008, pp. 157-160.
    18. The Fastest Modulo 2n±1 Adders, J. Biernat and J. Jablonski, Scientific Reports of the Institute of Engineering Cybernetics, Wroclaw University of Technology, No. 54, 2004.
    19. On the modulo 2n+1 multiplication for diminished-1 operands, C. Efstathiou, I. Voyiatzis and N. Sklavos, 2008 International Conference on Signals, Circuits and Systems, November 7-9, Hammamet, Tunisia, pp. 1-5.
    20. Improved Area-Efficient Weighted Modulo 2n+1 Adders Design with Simple Correction Schemes, T.-B.  Juang, C.-C. Chiu and M.-Y. Tsai, IEEE Transactions on Circuits and Systems II, to appear.
    21. Variation-Tolerant Design using Residue Number System, I. Kouretas and V. Paliouras, 12th Euromicro Conference on Digital System Design (DSD 2009), Patras, Greece, August 27-29, 2009, pp. 157-163.
    22. Design of Cost-Efficient Multipliers Modulo 2a-1, S. Piestrak, 2010 International Symposium on Circuits and Systems (ISCAS-2010), May 30 - June 2, 2010, to appear.