Citations

1. "Hybrid BIST for system-on-a-chip using an embedded FPGA core", Gang Zeng & Hideo Ito,in Proc. of IEEE VLSI Test Symposium, April 2004, pp.353-358.
2. "Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core", Gang ZENG1, Hideo ITO, IEICE Transactions on Information & Systems, vol E-88D, No5, pp. 984-992
3. "Increasing embedding probabilities of RPRPs in RIN based BIST", D.-S. Song, and S. Kang, Asia-Pacific Computer Systems Architecture Conference, LECT NOTES COMPUT SC 3740: 600-613, 2005.
4. "Reseeding using Compaction of Pre-Generated LFSR Sub-Sequences", Artur Jutman, Igor Aleksejev, Jaan Raik, Raimund Ubar, ICECS 2008, pp. 1290-1295