Citations

1. Diseno de un Sumador Digital de 32 bits para Circuitos Integrados, C. D. Martinez, Bachiller En Ingenieria Electrica, Universidad de Costa Rica, August 2004.
2. Analysis and Implementation of Binary Addition in Nanometer CMOS Technology, J. Grad, Ph.D. Thesis, Department of Electrical Engineering, Graduate College, Illinois Institute of Technology, May 2005.
3. An Efficient Architecture for Accumulator-Based Test Generation of SIC Pairs, I. Voyiatzis and C. Efstathiou, Microelectronics Journal, to appear.
4. An Efficient Architecture for Accumulator-Based Test Generation of SIC Pairs, I. Vogiatzis and C. Efstathiou, 2008 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS 2008), Tozeur, Tunisia, March 25-27, 2008, pp. 1-11.