Citations

1. S. Islam and M. Ali, "A Fast Seed Selection Technique for Cost Effective Hybrid Pattern Generation", Australian Journal of Electrical and Electronics Engineering, vol. 4, no. 2, pp. 147-158, 2008.
2. Abu-Issa and S. Quigley, "A Multi-Output Technique for High Fault Coverage in Test-per-Scan BIST" , Proc. of 3rd Int. Conference on Design and Technology of Integrated Systems in Nanoscale Era, pp. 1-6, March 2008.
3. D. -C. Yang, Y. -L. Xie and G. -J. Chen, "Built-in self-test for VLSI pipelined lattice digital filter", Acta Electronica Sinica, vol. 35, no. 11, pp. 2184-2188, November 2007.
4. H. Bing, Ch. Guang-Ju, X. Yong-Ie, "Two-Dimensional Test Data Compression Using Reseeding and Golomb Codes", Journal of Computer-Aided Design & Computer Graphics, vol. 17, no. 3, pp. 394-399, 2005.
5. S. Z. Islam, M. A. M. Ali & Md. L. Ali, "Development of an LFSR based test pattern generator for functional logic testing", Proceeedings of 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 591-594, December 2003.
6. M. A. M. Ali, S. Z. Islam & M. L. Ali, "Test processor chip design with complete simulation result including reseeding technique", Proceedings of IEEE International Conference on Semiconductor Electronics, pp. 218-221, December 2002.