Citations

1. An Efficient Test Strategy for Fast Multiplier Cores, J-C. Rau, C-H. Lin and C-H. Lin, Computational Methods in Circuits and Systems Applications, World Scientific and Engineering Academy and Society Press, 2003.
2. A Study on the Selection of LFSR's Characteristic Polynomial, W. Liu, Master of Science Thesis, National Chung Hsing University, College of Science, Dept. of Computer Science and Engineering, Taiwan, R.O.C, May 2002.
3. An Energy Efficient 32-bit Multiplier Architecture in 90-nm CMOS, N. Mehmood, M.Sc. Thesis, Linkoping Institute of Technology, Electronic Devices Division, September 2006.
4. Low-Power Multiplier using Input Data Partition, J. Park, J. Kim and W.-K. Cho, Korean Telecom Institute Journal, Vol. 30, No. 11A, November 2005, pp. 1092-1097.
5. A Low-Power Booth Multiplier using Novel Data Partition Method, J. Park, S. Kim and Y-S. Lee, IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC 2004), August 4-5, 2004, Fukuoka, Japan, pp. 54-57.
6. FPGAs: Excellent Platforms for SoC Testing R&D, C. E. Stroud, Invited Lecture in Series "Elevator Talks", International Test Conference (ITC 2008), Santa Clara, California, USA, October 26-31, 2008.