THE CEID STANDARD CELL LIBRARY

(Implemented on UMC 65nm Low Leakage Technology)

LIBRARY CELLS

Cell Size:

Driving strength	Channel Width
Driving strength	Library n-type transistors	Library p-type transistors
...X1	150nm	300nm
...X2	300nm	600nm
...X4	600nm	1.2um

A. Combinational Cells

Cell Name	Driving Strength			Cell Description
Cell Name	X1	X2	X4
INV	✓	✓	✓	Inverter
INVEN	✓	✓	✓	Tristate Inverter
BUF	✓	✓	✓	Buffer
BUFEN	✓	✓	✓	Tristate Buffer
NAND2	✓	✓	✓	2 Input NAND gate
AND2	✓	✓	✓	2 Input AND gate
NOR2	✓	✓	✓	2 Input NOR gate
OR2	✓	✓	✓	2 Input OR gate
XOR2	✓	X	X	2 Input XOR gate
XNOR2	✓	X	X	2 Input XNOR gate
AOI21	✓	✓	✓	And-Or-Inverter with one AND at the first level of two Inputs and one direct Input to the OR level
AOI211	✓	✓	✓	And-Or-Inverter with one AND at the first level of two Inputs and two direct Inputs to the OR level
AOI22	✓	✓	✓	And Or Inverter with two AND at the first level of two Inputs each
OAI21	✓	✓	✓	Or-And-Inverter with one OR at the first level of two Inputs and one direct Input to the AND level
OAI211	✓	✓	✓	Or-And-Inverter with one OR at the first level of two Inputs and two direct Inputs to the AND level
OAI22	✓	✓	✓	And-Or-Inverter with two OR at the first level of two Inputs each
MUX2	✓	X	X	Two to One bit Multiplexer
MUX4	✓	X	X	Four to One bit Multiplexer
MUX2B	✓	X	X	Two to One bit Multiplexer with negative output
FA1	✓	X	X	One bit Full Adder Cell
HA1	✓	X	X	One bit Half Adder Cell

B. Sequential Cells

Cell Name	Cell Description
QDLATE	Positive Enable triggered D type Latch
QDLATNE	Negative Enable triggered D type Latch
QDLATER	Positive Enable triggered D type Latch with Reset
QDLATNENR	Negative Enable triggered D type Latch with negative Reset
QDLATENS	Positive Enable triggered D type Latch with negative Set
QDLATNENS	Negative Enable triggered D type Latch with negative Set
QDLATESR	Positive Enable triggered D type Latch with Set and Reset
QDLATNESR	Negative Enable triggered D type Latch with Set and Reset
QDFFC	Positive clock triggered D type Flip-Flop
QDFFNC	Negative clock triggered D type Flip-Flop
QDFFCR	Positive clock triggered D type Flip-Flop with Reset
QDFFNCNR	Negative clock triggered D type Flip-Flop with negative Reset
QDFFCS	Positive clock triggered D type Flip-Flop with Set
QDFFNCNS	Negative clock triggered D type Flip-Flop with negative Set
QDFFCSR	Positive clock triggered D type Flip-Flop with Set and Reset
QDFFNCNSR	Negative clock triggered D type Flip-Flop with negative Set and Reset

C. Support Cells

Cell Name	Driving Strength			Cell Description
Cell Name	X1	X2	X4
TIE0	✓	✓	✓	Output is tight to logic '0'
TIE1	✓	✓	✓	Output is tight to logic '1'
FILL	✓	✓	✓	Placement gap filler cells

^{(CORTEX
M0DS)}DOWNLOAD THE LIBRARY

Download the Ceid Libs Via Definitions

!! The standard cell library is provided for academic and non profit use.
!! By downloading the library, you AGREE to use it according to
the statement above.
(If you use our library -- refer to our work)

Creator: Dr. Theodoros Simopoulos

STD Lib Views

Lib Driving Strengths

X1, X2, X4 Driving Strengths

16 Bit Set-Reset Register

16 Bit Adder_Subtracter

16 Bit Adder-Subtracter

16 Bit Comparison

16 Bit ALU
(Addition - Subtraction -Multiplication -
Division - Sqrt - Shift - Comparisson -
Bit wise units included)