The REIN project
Project research area
CMOS technology evolution has allowed the integration of a large number of cores on the die (System-on-Chip). However, shrinking geometries and greater design complexity has led to reliability challenges. One-time factory testing of VLSI circuits after fabrication is insufficient in the nanometer era, making periodic testing in the field necessary. Test data volume, test application time and power consumption during testing are critical parameters for both manufacturing as well as in the field testing. Variability, aging, power supply deviations and temperature effects can lead to intermittent faults and in some cases to catastrophic faults as well. Finally, technology scaling has increased the logic and SRAM memory susceptibility to radiation that leads to transient errors.
Project aims
1. Development of new test data compression and BIST techniques suitable for both manufacturing and several types of periodic testing, which will target small test data volume, small test application time and low-power consumption during testing.
2. Mitigation of transient faults in memory and logic circuits. Development of soft-error resilient and/or detection and correction techniques.
3. Mitigation of intermittent faults in logic circuits. Development of timing error detection and correction techniques.
4. Development of generalized low cost techniques for manufacturing and in-field testing as well as soft-error resilience.
Expected results
The development of unified approaches for reliability improvement targeting permanent, transient and intermittent faults, a crucial issue for the semiconductor industry in nanotechnology era.