[1]. S. Valadimas, Y. Tsiatouhas, A. Arapoyanni and P. Xarchakos, "Efficient Timing Error Tolerance in Flip-Flop Based Core Designs", Springer Journal of Electronic Testing Theory and Applications, vol. 29, no. 11, pp. 795-804, 2013.
[2]. P. Sismanoglou, and D. Nikolos, "Input test data compression based on the reuse of parts of dictionary entries: Static and dynamic approaches, IEEE Trans. CAD, vol. 32, no. 11, pp. 1762-1775, Nov. 2013.
[3]. E. Arvaniti and Y. Tsiatouhas, "Low Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique", Springer, Journal of Electronic Testing: Theory and Applications, vol. 30, pp. 329-341, 2014.
[4]. S. Valadimas, A. Floros, Y. Tsiatouhas, A. Arapoyanni and X. Kavousianos, "The Time Dilation Technique for Timing Error Tolerance",IEEE Trans. on Computers, vol. 63, no.5, pp. 1277-1285, 2014.
[5]. K. Katsarou and Y. Tsiatouhas, "Soft Error Interception Latch: A Double Node Charge Sharing SEU Tolerant Design", IET Electronics Letters, vol. 51, no. 4, pp. 330-332, 2015.
[6]. F. Vartziotis, X. Kavousianos, K. Chakrabarty, A. Jain, R. Parekhji, "Time-Division Multiplexing for Testing DVFS-based SoCs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.34, no.4, pp.668-681, 2015.
[7]. S. Valadimas, Y. Tsiatouhas and A. Arapoyanni, "Timing Error Tolerance in Small Core Designs for SoC Applications", IEEE Trans. on Computers, Accepted for publication, 2015.
[8]. N. Eftaxiopoulos, N. Axelos and K. Pekmestzi, "Radiation Tolerant Self-Repair Reconfigurable SRAM Architecture", Elsevier J. Microelectronics Reliability, Accepted for publication, 2015
[1]. P. Sismanoglou, and D. Nikolos, "Test data compression based on reuse of parts of dictionary entries", in Proc. 18th ICECS, pp. 538-541, 2011.
[2]. S. Valadimas, Y. Tsiatouhas and A. Arapoyanni, "Cost and Power Efficient Timing Error Tolerance in Flip-Flop Based Microprocessor Cores", IEEE European Test Symposium (ETS), pp. 8-13, May 2012.
[3]. S. Valadimas, Y. Tsiatouhas, A. Arapoyanni and A. Evans, "Single Event Upset Tolerance in Flip-Flop Based Microprocessor Cores", 16th IEEE Interνn Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 79-84, Oct. 2012.
[4]. M. Chalkia and Y. Tsiatouhas, "The Leafs Scan-Chain for Test Application Time and Scan Power Reduction", IEEE Intern. Conf. on Electronics, Circuits and Systems (ICECS), pp. 749-752, Dec. 2012.
[5]. A. Efthimiou, "An Error Tolerant CAM with NAND Match-Line Organization", ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 257-262, May 2013.
[6]. P. Sismanoglou and D. Nikolos, "Enhancing Dictionary based Test Data Compression using the ATE repeat instruction", in Proc 20th ICECS, Dec. 2013, pp. 401-404.
[7]. Eftaxiopoulos-Sarris, N.; Zervakis, G.; Tsoumanis, K.; Pekrnestzi, K., "A radiation tolerant and self-repair memory cell", in Proc. IEEE Intern. On-Line Testing Symposium, 2013, pp.210-215.
[8]. X. Kavousianos, K. Chakrabarty, "Testing for SoCs with Advanced Static and Dynamic Power-Management Capabilities", Invited Paper in Design Automation and Test in Europe Conference and Exhibition, DATE, 2013, pp. 737-742.
[9]. F. Vartziotis, X. Kavousianos, K. Chakrabarty, R. Parekhji, A. Jain, "Multi-Site Test Optimization for Multi-Vdd SoCs Using Space- and Time- Division Multiplexing", Design Automation and Test in Europe Conference and Exhibition, DATE, pages: 6, 2014.
[10]. P. Sismanoglou, and D. Nikolos, "Test Data Compression based on Reuse and Bit-Flipping of Parts of Dictionary entries", in Proc. 17th DDECS, April 2014, pp. 110-115.
[11]. X. Kavousianos, K. Chakrabarty, "Recent Advances in Single- and Multi-Site Test Optimization for DVS-based SoCs", Invited Paper in 9th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, Santorini, Greece, pages: 6, 2014.
[12]. K. Katsarou, Y. Tsiatouhas and A. Arapoyanni, "NBTI Aging Tolerance in Pipeline Based Designs", IEEE Intern. On-Line Testing Symposium (IOLTS), pp. 31-36, July 2013.
[13]. Anastasiou and Y. Tsiatouhas, "Power Efficient Scan Testing by Exploiting Existing Error Tolerance Circuitry in a Design", IEEE European Test Symposium (ETS), pages: 2, May 2014.
[14]. Axelos, N.; Eftaxiopoulos, N.; Zervakis, G.; Tsoumanis, K.; Pekmestzi, K., "FF-DICE: An 8T Soft-Error Tolerant Cell using Independent Dual Gate SOI FinFETs", in Proc. IEEE Intern. On-Line Testing Symposium, (IOLTS), 2014, Jul. 2014, pp.200-201.
[15]. N.Eftaxiopoulos, N.Axelos, G.Zervaskis, K.Tsoumanis, K.Pekmestzi, "An Independent Dual Gate SOI FinFET Soft-Error Resilient Memory Cell", IEEE Int. Design and Test Symp., Dec. 2014, pp.39-44.
[16]. H-M. Dounavi and Y. Tsiatouhas, "Stuck-at Fault Diagnosis in Scan Chains", 9th Intern. Conf. on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), pp. 96-101, May 2014.
[17]. K. Katsarou and Y. Tsiatouhas, "Double Node Charge Sharing SEU Tolerant Latch Design",IEEE Intern. On-Line Testing Symposium (IOLTS), pp. 122-127, July 2014.
[18]. P. Sismanglou, V. Pitsios, and D. Nikolos, "Preemptive built-in self-test for in-field structural testing", in Proc. of ISQED, March 2015, pp. 154-161. (nominated for best paper award)
[19]. K. Katsarou and Y. Tsiatouhas, "Soft Error Immune Latch Under SEU Related Double-Node Charge Collection", IEEE Intern. On-Line Testing Symposium (IOLTS), pp. 46-49, July 2015.
[20]. Anastasiou, Y. Tsiatouhas and A. Arapoyanni, "On the Reuse of Existing Error Tolerance Circuitry for Low Power Scan Testing", IEEE Intern. Symposium on Circuits and Systems (ISCAS), pp. 1578-1581, May 2015.
[21]. N.Eftaxiopoulos, N.Axelos and K.Pekmestzi, "Low Leakage Radiation Tolerant CAM/TCAM Cell", in Proc. IOLTS, pp. 206-211, July 2015.
[22]. N.Eftaxiopoulos, N.Axelos and K.Pekmestzi, "DONUT: A Double Node Upset Tolerant Latch", in Proc. ISVLSI, pp. 509-514, July 2015.
[23]. F. Vartziotis, X. Kavousianos, K. Chakrabarty, "A Branch-and-Bound Algorithm for TAM Optimization in Multi-Vdd SoCs", European Test Symposium (ETS), Romania, pages: 2, 2015.
[24]. F. Vartziotis, X. Kavousianos, P. Georgiou, K. Chakrabarty, "Test-Access-Mechanism Optimization for Multi-Vdd SoCs", International Test Conference (ITC), USA, pages: 6, 2015
[25]. P. Sismanoglou and D. Nikolos "Low Capture Power Dictionary based Test Data Compression", 17th Intern. Symposium on Quality Electronic Design (ISQED 2016), 14-16 March, 2016 Santa Clara, CA, USA, accepted.
[1]. N.Eftaxiopoulos, N.Axelos and K.Pekmestzi, "SRAM Memory Cell Radiation Induced Errors - Analysis and Study in the nm Era", J. Engineering Science & Technology Review, to appear.
[2]. N.Eftaxiopoulos, N.Axelos and K.Pekmestzi, "Bulk and IDG FinFET SOI Radiation Tolerant Cells (for SRAM and Latches)", J. Engineering Science & Technology Review, to appear.
[1]. S. Valadimas and A. Arapoyanni, "Timing Error Tolerance in Pipeline Based Core Designs", 18th Pan-Hellenic Conference on Informatics (PCI), pages: 6, October 2014.
[2]. K. Katsarou and Y. Tsiatouhas, "A Double Node Charge Sharing SEU Tolerant Latch", Pan-Hellenic Conference on Electronics and Telecommunications (PACET), pages: 3, May 2015.
[3]. S. Valadimas and A. Arapoyanni, "Low-Power & Cost-Effective Timing Error Tolerance in Flip-Flop Based Microprocessor Cores", Pan-Hellenic Conference on Electronics and Telecommunications (PACET), pages: 4, 8-9 May 2015.
[4]. S. Valadimas and A. Arapoyanni, "Timing Error Tolerance in Pulsed Latch Based Pipelines", Pan-Hellenic Conference on Electronics and Telecommunications (PACET), pages: 4, 8-9 May 2015.
[5]. F. Vartziotis, X. Kavousianos, P. Georgiou, K. Chakrabarty, "TAM Optimization for Multi-Vdd SoCs based on a Branch and Bound Algorithm", Pan-Hellenic Conference on Electronics and Telecommunications (PACET), pages: 2, 8-9 May, 2015.
[6]. N.Eftaxiopoulos, N.Axelos and K.Pekmestzi, "SRAM Memory Cell Radiation Induced Errors - Analysis and Study in the nm Era", in Proc. Pan-Hellenic Conference on Electronics and Telecommunications (PACET), pages: 4, 8-9 May 2015.
[7]. N.Eftaxiopoulos, N.Axelos and K.Pekmestzi, "Bulk and IDG FinFET SOI Radiation Tolerant Cells (for SRAM and Latches)", in Proc. Pan-Hellenic Conference on Electronics and Telecommunications (PACET), pages: 4, 8-9 May 2015.
[8]. P. Sismanoglou, and D. Nikolos, "On Dictionary based Test Data Compression", 3rd in Proc Pan-Hellenic Conference on Electronics and Telecommunications (PACET), pages: 2, 8-9 May 2015.
[9]. H-M. Dounavi, Y. Tsiatouhas and A. Arapoyanni, "Scan Chain Based At-Speed Diagnosis in the Presence of Scan Output Compaction Schemes", 19th Pan-Hellenic Conference on Informatics (PCI), pp. 419-423 , October 2015.