Advanced Topics on Computer Architecture

Syllabus

This course focuses on understanding and implementing the principles of pipelining in modern processors, starting from foundational theory and progressing to advanced techniques for maximizing Instruction-Level Parallelism (ILP). Students will study the design of a pipelined datapath in processors based on the RISC-V instruction set architecture, the construction of the pipeline control unit, and the various types of hazards (structural, data, and control), along with techniques for their avoidance and resolution, such as forwarding (bypassing), branch prediction, and delayed branching. Special attention is given to exception handling in pipelined systems, advanced branch prediction, and dynamic instruction execution. The course introduces students to the philosophy of superscalar architectures with multiple instruction issue, and to techniques such as reservation stations and register renaming, as introduced by Tomasulo’s algorithm. Students will develop an understanding of how out-of-order execution improves performance by enhancing the utilization of available computational units.

In parallel, the course explores instruction and data prefetching techniques that contribute to reducing memory access latency. Students will examine ways to optimize the memory hierarchy, with a focus on cache design and virtual memory to enhance program performance. Finally, the course covers the interconnection of processors, main memory, and peripheral devices via buses, and examines how the operating system collaborates with I/O units. By combining theory, practical examples, and modeling of modern techniques through laboratory exercises, the course aims to provide students with a comprehensive understanding of the internal operation of modern processors and their integration into the broader computing system.

Upon successful completion of the course, students will be able to:

1. Explain the fundamental principles of pipelining and describe how they are applied in processors such as RISC-V.
2. Identify and classify the different types of hazards that occur during pipelined program execution, and propose appropriate resolution techniques (e.g., forwarding, inserting stalls, branch prediction).
3. Analyze and evaluate the operation of dynamic branch prediction techniques.
4. Understand and describe the basic concepts of out-of-order execution, and explain how they are implemented in modern architectures using Tomasulo’s algorithm, reservation stations, and reorder buffers.
5. Design or modify processor models with multiple instruction issue.
6. Explain the role and significance of prefetchers (instruction and/or data prefetching units), and evaluate their impact on reducing memory latency.
7. Analyze memory system performance, including cache hierarchy and virtual memory, using metrics such as hit rate, miss penalty, and average memory access time (AMAT).
8. Compare different processor architectures in terms of performance, reliability, and implementation complexity.