Computer Architecture Laboratory

Syllabus

The Computer Architecture Laboratory is a practice-oriented course that complements and reinforces the theoretical instruction of computer architecture. Through a series of targeted laboratory exercises, students gain hands-on experience in developing, executing, and debugging RISC-V assembly language programs, as well as in understanding the internal operation of modern processors. The course is built around two educational simulators, RARS and Ripes, offering students both programming practice at the Instruction Set Architecture (ISA) level and visual insight into processor internals.

In the initial exercises, students become familiar with the RARS simulator, focusing on assembly translation, monitoring registers and memory, and controlling program execution. They strengthen their understanding of basic arithmetic and logical operations, carry management, and algorithm implementation using RISC-V assembly language. The course then advances to more complex topics such as procedure calls using the stack, memory management with pointers and the heap, and exception handling.

The second part of the course shifts focus to the microarchitectural aspects of instruction execution, using the Ripes simulator. Students have the opportunity to observe step-by-step the flow of instructions through the stages of a processor (fetch, decode, execute, memory, writeback) and to compare single-cycle and pipelined processor implementations. Through exercises that combine data dependency analysis and instruction reordering, students develop a deep understanding of performance optimization techniques and the role of hardware design in execution speed.

Overall, the course strengthens the connection between low-level programming and hardware operation, preparing students for further study in areas such as compilers, operating systems, and digital system design.

Upon successful completion of the course, students will be able to:

1. Develop, debug, and execute RISC-V assembly language programs using the RARS simulator.
2. Apply basic and advanced arithmetic and logical instructions of the RISC-V instruction set, demonstrating an understanding of concepts such as carry, overflow, and internal data representation.
3. Manage the stack and heap to implement procedures and dynamic data structures, applying the calling conventions of the RISC-V architecture.
4. Understand and handle exceptions during program execution by utilizing the architectural support provided by RISC-V.
5. Observe and analyze the instruction flow within a processor using the visualization features of Ripes, identifying dependencies and applying optimization techniques.
6. Compare different microarchitectural implementations of processors (single-cycle and pipelined designs), recognizing their impact on overall program performance.