Publications





International Journals


ACM Transactions on Design Automation of Electronic Systems

1.

Efficient Partial Scan Cell Gating for Low Power Scan-based Testing, X. Kavousianos, D. Bakalis and D. Nikolos, ACM Transactions on Design Automation of Electronic Systems, Vol. 14, No. 2, Article 28, March 2009, pages 15.

+Citations(1)

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IEEE Transactions on Computers

2.

An Improved Search Method for Accumulator-Based Test Set Embedding, D. Nikolos, D. Kagaris, S. Sudireddy and S. Gidaros, IEEE Transactions on Computers, Vol. 58, N.1, Jan. 2009, pp. 132-138.

+Citations(1)

3.

Optimal Selective Huffman Coding for Test Data Compression, X. Kavousianos, E. Kalligeros and D. Nikolos, IEEE Transactions on Computers, Aug. 2007, Vol. 56, N.8, pp.1146-1152.

+Citations(7)

4.

Efficient Diminished-1 Modulo 2n+1 Multipliers, C. Efstathiou, H. T. Vergos, G. Dimitrakopoulos, and D. Nikolos, IEEE Transactions on Computers, vol. 54, no. 4, April 2005, pp. 491-496.

+Citations(15)

5.

High-Speed Parallel-Prefix VLSI Ling Adders, G. Dimitrakopoulos, and D. Nikolos, IEEE Transactions on Computers, Volume: 5, Issue: 2, Feb. 2005, pp. 225 - 231.

+Citations(44)

6.

Fast Parallel-Prefix Modulo 2n + 1 Adders, C. Efstathiou, H. T. Vergos, and D. Nikolos, IEEE Transactions on Computers, Sept. 2004, pp. 1211-1216.

+Citations(29)

7.

Modified Booth Modulo 2n - 1 Multipliers, C. Efstathiou, H. T. Vergos, and D. Nikolos, IEEE Transactions on Computers, VOL. 53, No. 2 March 2004, pp.370-374.

+Citations(21)

8.

Modulo 2ną1 Adder Design Using Select-Prefix Blocks, C. Efstathiou, H. T. Vergos & D. Nikolos, IEEE Transactions on Computers, Vol. 52, No. 11, November 2003, pp. 1399-1406.

+Citations(22)

9.

Deterministic BIST for RNS Adders", H. T. Vergos, D. Nikolos, M. Bellos and C. Efstathiou, IEEE Transactions on Computers, July 2003, pp.896-906.

10.

"Diminished-One Modulo 2n+1 Adder Design", H. T. Vergos, C. Efstathiou and Nikolos, IEEE Transactions on Computers, Dec. 2002, pp. 1389-1399.

+Citations(27)

11.

 

"High-Speed Parallel-Prefix Modulo 2n-1 Adders" L. Kalampoukas, D. Nikolos, C. Efstathiou, H. T. Vergos, & J. Kalamatianos, IEEE Transactions on Computers, Special Issue on Computer Arithmetic, July 2000, pp. 673-680.

+Citations(50)

12.

"On the Yield of VLSI Processors with On-Chip CPU Cache", D. Nikolos, H.T. Vergos, IEEE Trans. on Computers, October 1999, pp.1138-1144.

+Citations(6)

13.

"Optimal Self-Testing Embedded Parity Checkers", D. Nikolos, IEEE Trans. on Computers, March 1998, pp. 313-321.

+Citations(13)

14.

 

"Efficient Totally Self-Checking Checkers for a Class of Borden Codes", Th. Haniotakis, A. Paschalis and D. Nikolos, IEEE Trans. on Computers, VOL. 44, NO. 11, November 1995, pp. 1318-1322.

+Citations(9)

15.

"On TSC checkers for m-out-of-n codes", V. Dimakopoulos, G. Sourtziotis, A. Paschalis and D. Nikolos, IEEE Trans. on Computers, VOL. 44, NO. 8, August 1995, pp. 1055-1059.

+Citations(12)

16.

 

"Theory and Design of t-Error Correcting, k-Error Detecting and d-Unidirectional Error Detecting Codes with d>k>t.", D. Nikolos, and A. Krokos. IEEE Trans. on Computers, April 1992, pp. 411-419.

+Citations(5)

17.

 

"Theory and Design of t-Error Correcting/d-Error Detecting (t<d) and All Unidirectional Error Detecting Codes.", D. Nikolos, IEEE Transactions on Computers, Vol. 40, No 2, February 1991, pp. 132-142.

+Citations(13)

18.

 

"Efficient Design of Totally Self-Checking Checkers for All Low-Cost Arithmetic Codes". D. Nikolos, A. Paschalis and G. Philokyprou. IEEE Transactions on Computers vol. 37, no. 7, July 1988, pp. 807-814.

+Citations(30)

19.

"Efficient Modular Design of TSC Checkers for M-out-of-2M Codes", A.Paschalis, D. Nikolos and K. Halatsis. IEEE Transactions on Computers vol. 37, no. 3, March 1988, pp. 301-309.

+Citations(38)

20.

 

"Systematic t-Error Correcting/All Unidirectional Error Detecting Codes", D. Nikolos, N. Gaitanis and G. Philokyprou, IEEE Transactions on Computers Vol. C-35, No. 5, May 1986 pp. 394-402.

+Citations(55)

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IEEE Transactions on Computer Aided Design

21.

Test-Data Compression Based on Variable-to-Variable Huffman Encoding with Codeword Reusability, X. Kavousianos, E. Kalligeros, D. Nikolos, IEEE Trans. on Computer- Aided Design, Jul. 2008, vol. 27, n. 7, pp.1333-1338.

+Citations(2)

22.

Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores, X. Kavousianos, E. Kalligeros and D. Nikolos, IEEE Trans. on Computer- Aided Design, June 2007, Vol. 26, N. 6, pp.1070-1083.

+Citations(10)

23.

On Obtaining Maximum Length Sequences for Accumulator-Based Serial TPG, D. Kagaris, P. Karpodinis, and D. Nikolos, IEEE Trans. on Computer- Aided Design, VOL. 25, No. 11, Nov. 2006 pp. 2578-2586.

+Citations(1)

24.

"Multi-phase BIST: A New Reseeding Technique for High Test Data Compression", E. Kalligeros, X. Kavousianos and D. Nikolos, October 2004, pp. 1429 - 1446.

+Citations(6)

25.

"A new Built-In TPG Method for Circuits with Random Pattern Resistant Faults", X. Kavousianos, D. Bakalis, D. Nikolos and S. Tragoudas, July 2002, pp. 859-866.

+Citations(1)

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IEEE Transactions on VLSI Systems

26.

Multilevel-Huffman Test-Data Compression for IP Cores with Multiple Scan Chains, X, Kavousianos, E. Kalligeros, and D. Nikolos, IEEE Trans. on VLSI Systems, pp. 926-931.

+Citations(4)

27.

Low-Power Leading Zero Counting and Anticipation Logic for High-Speed Floating Point Units, G. Dimitrakopoulos, K. Galanopoulos, C. Mavrokefalidis and D. Nikolos, IEEE Trans. on VLSI Systems, pp.837-850.

28.

Sorter Based Permutation Units for Media-Enhanced Microprocessors, G. Dimitrakopoulos, C. Mavrokefalidis, K. Galanopoulos and D. Nikolos, IEEE Trans. on VLSI Systems, June 2007, Vol. 15, N. 6, pp.711-715.

+Citations(3)

29.

Testable Designs of Multiple Precharged Domino Circuits, Th. Haniotakis, Y. Tsiatouhas, D. Nikolos and C. Efstathiou, IEEE Trans. on VLSI Systems, April 2007, Vol. 15, N. 4, pp. 461 - 465.

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IEEE Transactions on Circuits and Systems.

30.

"Area-Time Efficient Modulo 2n-1 Adder Design" C. Efstathiou, D. Nikolos and J. Kalamatianos, IEEE Trans. on Circuits and Systems, July 1994, pp. 463-467.

+Citations(22)

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IEE Proceedings on Computers & Digital Techniques.

31.

 

"Linear-Testable and C-Testable NX x NY Modified Booth Multipliers" D. Gizopoulos, A. Paschalis, D. Nikolos and C. Halatsis, IEE Proceedings, Computers and Digital Techniques, Vol. 143, No.1 January 1996, pp. 44-48.

+Citations(4)

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International Journal of Electronics.

32.

 

Domino CMOS SCD/SFS 2-out-of-3 and 1-out-of-3 Code Checkers, Th. Haniotakis, Y. Tsiatouhas, C. Efstathiou and D. Nikolos, International Journal of Electronics, Volume 90, Number 2, Feb. 2003, pp. 145-158.

33.

Handling Zero in Diminished-One Modulo 2n+1 Adders, C. Efstathiou, H. T. Vergos & D. Nikolos, International Journal of Electronics, Volume 90, Number 2, Feb. 2003, pp. 133-144.

+Citations(2)

34.

 

"Path delay fault testing of multiplexer-based shifters", H. T. Vergos, Y. Tsiatouhas, Th. Haniotakis, D. Nikolos & M. Nicolaidis, International Journal of Electronics, Vol. 88, No. 8, August 2001, pp. 923-937.

35.

 

"On Robust Two-Pattern Testing of One-Dimentional CMOS Iterative Logic Arrays", D. Gizopoulos, A. Paschalis. D. Nikolos & C. Halatsis, International Journal of Electronics, August 1999, Vol. 86, No 8, pp. 967-978.

36.

 

"Hierarchical Robust Test Generation For CMOS Circuit Stuck-Open Faults" Y. Tsiatiouhas, Th. Haniotakis, D. Nikolos, A. Paschalis, and C. Halatsis, International Journal of Electronics, 1997, vol. 82, no. 1, pp.45-60.

+Citations(1)

37.

"Fast C-Testable Array Multipliers", D. Gizopoulos, D. Nikolos and A. Paschalis, International Journal of Electronics,Vol. 80, No. 4, 1996, pp. 561-582.

+Citations(3)

38.

 

"Robust Test Generation for Transistor Stuck-Open Faults in CMOS Complex Gates",G. Tsiatouhas, A. Paschalis, D. Nikolos and C. Halatsis, International Journal of Electronics, 1995, VOL. 79, NO. 2, pp. 129-142.

39.

"Totally self-checking checkers for Borden Codes", Th. Haniotakis, D. Nikolos, A. Paschalis and D. Gizopoulos, Int. J. Electronics, 1994, Vol. 76, No. 1. pp. 57-64.

+Citations(1)

40.

 

"Fast and low cost TSC checkers for 1-out-of-n and (n-1)-out-of-n codes in MOS transistor implementation", T. Haniotakis, A. Paschalis and D. Nikolos, Int. J. Electronics, 1991, Vol.71, No 5, pp. 781-791.

+Citations(4)

41.

 

"New Design method for Low-Cost TSC Checkers for 1-out-of-N /(N-1)-out-of-? Codes in MOS Transistor Implementation". G. B. Laskaris, T. N. Haniotakis, A. M. Paschalis and D. Nikolos, International Journal of Electronics, June 1990, pp. 805-817.

+Citations(2)

42.

"t-symmetric and d-unidirectional (t<d) error detecting cyclic AN arithmetic codes". D. Nikolos, (invited paper), January 1990, vol. 68 No. 1, pp. 1-22.

+Citations(1)

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Integration: The VLSI Journal.

43.

 

"A New Technique for IDDQ Testing in Nanometer Technologies" by Y. Tsiatouhas, Y. Moisiadis, Th. Haniotakis, D. Nikolos and A. Arapoyanni, Integration, the VLSI Journal 31(2002) pp. 183-194.

+Citations(2)

44.

"New efficient totally self-checking Berger code checkers", X. Kavousianos, D. Nikolos, G. Foukarakis and T. Gnardelis, Integration: the VLSI Journal 28 (1999), pp.101-118.

+Citations(1)

45.

 

"Testing CMOS Combinational Iterative Logic Arrays For Realistic Faults", D. Gizopoulos, D. Nikolos and A. Paschalis. Integration, the VLSI Journal, vol. 21, no. 3, December 1996, pp. 209-228.

+Citations(5)

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Journal of Electronic Testing

46.

 

"On-the-Fly Reseeding: A New Reseeding Technique for the Test-per-Clock BIST", E. Kalligeros, X. Kavousianos, D. Bakalis and D. Nikolos, Journal of Electronic Testing: Theory and Applications, June 2002, pp. 315-332.

+Citations(5)

47.

 

"An Accumulator-Based BIST Approach for Two-Pattern Testing", I. Voyiatzis, A. Paschalis, D. Nikolos and C. Halatsis, Journal of Electronic Testing: Theory and Applications, December 1999, pp.267-278.

+Citations(1)

48.

"Self-Testing Embedded Two-Rail Checkers", D Nikolos, Journal of Electronic Testing: Theory and Applications (JETTA), Feb./Apr. 1998, pp.69-79.

+Citations(4)

49.

"C- Testable Modified - Booth Multipliers", D. Gizopoulos, D. Nikolos, A. Paschalis, and C. Halatsis, Journal of Electronic Testing: Theory and Applications 8, 1996, pp. 241-260.

+Citations(9)

50.

"An Efficient Built-In Self-Test Method for Robust Path Delay Fault Testing", J. Voyiatzis, A. Paschalis, D. Nikolos and C. Halatsis, Journal of Electronic Testing, 8, 1996, pp. 219-222.

+Citations(6)

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Journal of Systems Architecture

51.

 

"A Core Generator for Arithmetic Cores and Testing Structures with a network interface" D. Bakalis,  K. D. Adaos, D. Lymperopoulos, M. Bellos, H.T. Vergos, G. Alexiou, D. Nikolos, Journal of Systems Architecture (JSA) 52 (2006), pp.1-12 .

+Citations(4)

52.

 

"On the Design of Low Power BIST for Multipliers with Booth Encoding and Wallace Tree Summation", D. Bakalis, E. Kalligeros, D. Nikolos, H. T. Vergos, G. Alexiou, JSA 48 (2002) p.125-135.

+Citations(1)

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The Euromicro Journal

53.

"Efficient Fault Tolerant Cache Memory Design", H.T. Vergos and D. Nikolos, Microprocessing and Microprogramming, The Euromicro Journal, 41 (1995) pp. 153-169.

+Citations(7)

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VLSI Design

54.

 

"Low Power Built-In Self-Test Schemes for Array and Booth Multipliers" D. Bakalis, X. Kavousianos, H. T. Vergos, D. Nikolos and G. Ph. Alexiou, VLSI Design: Special Issue on Low Power Architecture Design, Vol. 12, No. 3, 2001, pp. 431-448.

55.

"Novel Single and Double Output TSC CMOS Checkers for m-out-of-n Codes", X. Kavousianos, D. Nikolos, G. Sidiropoulos, VLSI Design, Vol. 11, No. 1, 2000, pp. 35-45.

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Books

56.

 

"Design and Analysis of On-Chip CPU Pipelined Caches", C. Ninos, H.T. Vergos, D. Nikolos, in VLSI: Systems On A Chip, eds. by L.M. Silveira, S. Devadas and R. Reis, Kluwer Academic Publishers, 2000, pp.161-172.

57.

 

"Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks", M. Bellos, D. Nikolos and H.T. Vergos, in Dependable Computing - EDCC-3 ( Lecture Notes in Computer Science, 1667) eds. J. Hlavicka and E. Maehle, Springer, 1999, pp.267-282.

58.

"Self-Testing Embedded Two-Rail checkers", D. Nikolos, in On-Line Testing for VLSI, edited by M. Nicolaidis, Y. Zorian and D.J. Pradhan, Kluwer Academic Publishers, 1998.

59.

 

"Reconfigurable CPU Cache Memory Design: Fault Tolerance and Perfomance Evaluation", H.T. Vergos, D. Nikolos, P. Mitsiadis and C. Kavousianos in VLSI: Integrated Systems on Silicon, eds. by R. Reis and L. Claesen, Chapman & Hall, 1997, pp.101-114.

60.

 

" On the Yield of VLSI Processors with on-chip Cache", D. Nikolos and H. T. Vergos, Proc. of Second European Dependable Computing Conference (EDCC-2), Taormina, Italy, Oct. 2-4, 1996, pp. 214-229. (Lecture Notes in Computer Science, Springer-Verlag).

61.

 

"Theory and Design of t-Error Correcting/d-Error Detecting (d>t) and All Unidirectional Error Detecting Codes", D. Nikolos, in Codes for Detecting and Correcting Unidirectional Errors, editor M. Blaum, IEEE Computer Society Press, 1993, pp.135-145.

62.

 

"On t-Error Correcting and d-Unidirectional Error Detecting Codes with dt", D. Nikolos and A. Krokos, in Hardware & Software Dault Tolerance in Parallel Computing Systems, editor D.R. Avresky, Ellis Horwood, 1992, pp.327-334.

63.

 

"Efficient Design of Totally Self-Checking Checkers for All Seperate Low Cost Arithmetic Codes", D. Nikolos, A.M. Paschalis and G. Philokyprou, (edited by S. Tzafestas, M. Singh and G. Schmidt), System Fault Diagnostics, Reliability and Related Knowledge-Based Approaches, vol. 2, D. Reidel Publishing.

64.

 

"A Fault Tolerant Dynamic RAM Memory System", D. Nikolos, P. Kostarakis and A.M. Paschalis, (edited by S. Tzafestas, M. Singh and G. Schmit), System Fault Diagnostics, Reliability and Related Knowledge-Based Approaches, vol. 2, D. Reidel Publishing Company, 1987, pp.301-308.

65.

 

"Efficient Modular Design of TSC Checkers for M-out-of-2M Codes", A.M. Paschalis, D. Nikolos and C.Halatsis, (edited by F. Makedon, K. Melhorn, T. Papatheodorou and P. Spirakis), VLSI Algorithms and Architectures, Lecture Notes in Computer Science, vol. 227, Springer-Verlang, 1986, pp.144-155.

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International Conferences

66.

 

M. Koutsoupia, E. Kalligeros, X. Kavousianos, and D. Nikolos, LFSR-based Test-Data Compression with Self-Stoppable Seeds, in Proc. of Design Automation and Test in Europe, (DATE), 20-24 April, 2009, Nice, France pp. 1482-1487.

67.

 

X. Kavousianos, E. Kalligeros and D. Nikolos, Test-Data Compression Based on Variable-to-Variable Reusable Huffman Coding, in Informal, Digest of Papers of IEEE European Test Symposium, May 2006 pp. 433-438.

68.

 

G. Dimitrakopoulos, Ch. Mavrokefalidis, K. Galanopoulos and D. Nikolos, An Energy Delay Efficient Subword Permutation Unit, Proc. of the IEEE 17th International Conference on Aplication-Specific Systems, Architectures and Processors (ASAP), Sept. 11-13, 2006 Steamboat Springs, Colorado, USA, pp. 245-250.

69.

 

D. Nikolos, D. Kagaris and S. Gidaros, Diophantine-Equation Based Arithmetic Test Set Embedding, Proc. of the 12th IEEE International On-Line Testing Symposium, Lake of Como, Italy, July 10-12, 2006, pages: 2

+Citations(4)

70.

 

X. Kavousianos, E. Kalligeros and D. Nikolos, "A Parallel Multilevel-Huffman Decompression Scheme for IP Cores with Multiple Scan Chains", in Informal Digest of Papers of IEEE European Test Symposium, May 2006, pp. 164-169.

71.

 

G. Dimitrakopoulos, Ch. Mavrokefalidis, K. Galanopoulos and D. Nikolos, Fast Bit Permutation Unit for Media Enhanced Microprocessors, Proc. of the the IEEE International Symposium on Circuits and Systems (ISCAS'06), May 21-24, 2006 Island of Kos, Greece, pages: 4

72.

 

E. Kalligeros, X. Kavousianos and D. Nikolos, "Efficient Multiphase Test Set Embedding for Scan-based Testing", in Proc. of 7th IEEE International Symposium on Quality Electronic Design (ISQED' 06), San Jose, CA, USA, March 27-29, 2006, pp. 433-438.

+Citations(1)

73.

 

X. Kavousianos, E. Kalligeros and D. Nikolos, "Efficient Test-Data Compression for IP Cores Using Multilevel Huffman Coding", in Proc. of Design Automation and Test in Europe, (DATE), 6-10 March, 2006, Munich, Germany, pages: 6.

+Citations(4)

74.

 

G. Dimitrakopoulos, D. G. Nikolos, H. T. Vergos, D. Nikolos and C. Efstathiou, "New Architectures for Modulo 2^n-1 Adders", in Proc. of 12th IEEE Int. Conference on Electronics, Circuits and Systems, Gammarth, Tunisia, Dec. 11-14th, 2005.

+Citations(2)

75.

 

G. Gekas, D. Nikolos, E. Kalligeros and X. Kavousianos, "Power Aware Test-Data Compression for Scan-based Testing", in Proc. of 12th IEEE Int. Conference on Electronics, Circuits and Systems, Gammarth, Tunisia, Dec. 11-14th, 2005.

76.

 

D. Kaseridis, E. Kalligeros, X. Kavousianos and D. Nikolos, "An Efficient Test Set Embedding Scheme with Reduced Test Data Storage and Test Sequence Length Requirements for Scan-based Testing", IEEE European Test Symposium (ETS 2005) Tallin, Estonia, May 22-25, (poster).

77.

 

M. Bellos and D. Nikolos, "Deterministic Test Vector Compression / Decompression Using an Embedded Processor" Proc. of Fifth European Dependable Computing Conference (EDCC-5), Budapest, Hungary, April 20-22, pp. 318-331.

78.

 

E. Kalligeros, D. Kaseridis, X. Kavousianos and D. Nikolos, "Reseeding-based Test Set Embedding with Reduced Test Sequences" " in Proc. of 6th IEEE International Symposium on Quality Electronic Design (ISQED' 05), San Jose, CA, USA, March 21-23, 2005, pp. 226-231.

+Citations(5)

79.

 

P. Karpodinis, D. Kagaris, D. Nikolos, "Accumulator based Test-per-Scan BIST", in Proc. of 10th International On-Line Testing Symposium, Funchal, Madeira Island, Portugal, July 12-14, 2004, pp. 193-198.

80.

 

C. Laoudias and D. Nikolos, "A New Test Pattern Generator for High Defect Coverage in a BIST Environment", In Proc. of the 2004 ACM Great Lakes Symposium on VLSI (GLSVLSI'04), Boston MA, April 26-28, 2004 pp. 417-420

81.

 

X. Kavousianos, D. Bakalis, M. Bellos and D. Nikolos, "An Efficient Test Vector Ordering Method for Low Power Testing", in Proc. of IEEE International Symposium on VLSI (ISVLSI?04), Lafayette, LA, USA, February 19-20, 2004, pp. 285-288.

+Citations(6)

82.

 

M. Bellos, D. Bakalis, and D. Nikolos, "Scan Cell Ordering for Low Power BIST", in Proc. of IEEE International Symposium on VLSI (ISVLSI?04), Lafayette, LA, USA, February 19-20, 2004, pp. 281-284.

+Citations(5)

83.

 

M. Bellos, D. Bakalis, D. Nikolos, and X. Kavousianos, "Low Power Testing by Test Vector Ordering With Vector Repetition" in Proc. of 5th IEEE International Symposium on Quality Electronic Design (ISQED' 04), San Jose, CA, USA, March 22-24, 2004, pp.205-210.

+Citations(6)

84.

DV-TSE: Difference Vector Based Test Set Embedding, M. Bellos, D. Nikolos, X. Kavousianos and D. Kagaris, in Proc. of the IFIP VLSI-SoC 2003 Conference, pp. 343- 348.

85.

 

An Efficient BIST scheme for High-Speed Adders, D. G. Nikolos, D. Nikolos, H. T. Vergos and C. Efstathiou, Proc. of the 9th IEEE Int. On-Line Tesing Symposioum (IOLTS 2003), Kos, Greece, 7-9 July 2003, pp. 89-93.

+Citations(1)

86.

 

A family of Parallel-Prefix Modulo 2n-1 Adders, G. Dimitrakopoulos, H. T. Vergos, D. Nikolos and C. Efstathiou, Proc. of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2003), Leiden, The Netherlands, 24-26 June 2003, pp. 326-336.

+Citations(5)

87.

 

G. Dimitrakopoulos, X. Kavousianos, and D. Nikolos, "Virtual-Scan: A Novel Approach for Software-Based Self-Testing of Microprocessors", Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS'03), May 2003, Bangkok, Thailand, pp.V-237 - V-240.

88.

 

G. Dimitrakopoulos, H. T. Vergos, D. Nikolos, and C. Efstathiou, "A Systematic Methodology for Designing Area-Time Efficient Parallel-Prefix Modulo 2n-1 Adders", Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS' 03), May 2003, Bangkok, Thailand, pp. V-225 - V-228.

+Citations(2)

89.

 

Efficient BIST Schemes for RNS Datapaths, D. G. Nikolos, D. Nikolos H. T. Vergos & C. Efstathiou, Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS) , Bangkok, Thailand, May 25-28, 2003, pp. V-573 - V-576.

90.

 

"A Highly Regular Multi-phase Reseeding Technique for Scan-Based BIST", E Kalligeros, X. Kavousianos and D. Nikolos, in Proc. of the 2003 Great Lakes Symposium on VLSI (GLSVLSI 2003), April 28-29 2003, Washington D.C. USA, pp. 295-298.

+Citations(1)

91.

 

"Low Power Test Set Embedding Based on Phase Shifters", M. Bellos, D. Kagaris and D. Nikolos, in Proc of the IEEE Annual Symposium on VLSI (ISVLSI-03), Tampa, Florida, USA, February 20-21, 2003, pp. 155-160.

92.

"A ROM less LFSR Reseeding Scheme for Scan-based BIST" E. Kalligeros, X. Kavousianos and D. Nikolos, Proc. of the Tenth Asian Test Symposium (ATS'02), pp. 206-211.

+Citations(4)

93.

 

"Test Set Embedding Based on Phase Shifters", M. Bellos, D. Kagaris and D. Nikolos, Proc. of Fourth European Dependable Computing Conference (EDCC-4), ( LNCS 2485 Springer) Toulouse, France, Oct. 9-11. 2002, pp. 90-101.

94.

 

"Ling Adders in CMOS standard cell technologies", C. Efstathiou, H. T. Vergos & D. Nikolos, Proc. of the 9th IEEE International Conference on Electronics, Circuits & Systems, (ICECS 2002), September 15 - 18 2002, Dubrovnik, Croatia, pp. 485-488.

+Citations(4)

95.

 

Fast Parallel-Prefix Modulo 2n+1 adders, H. T. Vergos, C. Efstathiou & D. Nikolos, XVII Conference on Design of Circuits and Integrated Systems(DCIS' 2002), November 19-22, 2002, Santander, Spain, pp. 65-70.

+Citations(1)

96.

 

"Extending the Viability of IDDQ Testing in the Deep Submicron Era", Y. Tsiatouhas, Th. Haniotakis, D. Nikolos, and A. Arapoyanni, 3rd IEEE International Symposium on Quality Electronic Design (ISQED' 03), San Jose, CA, USA, March 18-20, 2002, pp. 100-105.

+Citations(4)

97.

 

"An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST", E. Kalligeros, X. Kavousianos, D. Bakalis, and D. Nikolos, 3rd IEEE International Symposium on Quality Electronic Design (ISQED' 03), San Jose, CA, USA, March 18-20, 2002, 261-266.

+Citations(6)

98.

 

"On the Design of Modulo 2ną1 Adders", C. Efstathiou, H. T. Vergos & D. Nikolos, 8th IEEE International Conference on Electronics, Circuits & Systems, (ICECS 2001), September 2 - 5 2001, Malta, Vol. I, pp. 517 - 520.

+Citations(2)

99.

 

H. T. Vergos, C. Efstathiou & D. Nikolos, " High Speed Parallel-Prefix Modulo 2n+1 Adders for Deminished One Operands", Proc. of 15th IEEE Symposium on Computer Arithmetic, June 11-13, 2001, Vail, Colorado, 211-217.

+Citations(6)

100.

 

X. Kavousianos, D. Bakalis and D. Nikolos, "A Novel Reseeding Technique for Accumulator-based Test Pattern Generation", 11th Great Lakes Symposium on VLSI (GLSVLSI'01), West Lafayette, IN, USA, March 22-23, 2001, pp. 7-12.

+Citations(1)

101.

 

D. Bakalis, D. Nikolos, H. T. Vergos and X. Kavousianos, "On Accumulator-based Bit-Serial Test Response Compaction Schemes", 2nd IEEE International Symposium on Quality Electronic Design (ISQED'01), San Jose, CA, USA, March 26-28, 2001, pp. 350-355.

+Citations(1)

102.

 

D. Bakalis, D. Nikolos and X. Kavousianos, "Test Response Compaction by an Accumulator Behaving as a Multiple Input Non-Linear Feedback Shift Register", Proc. of International Test Conference (ITC'00), pp. 804-811, Atlantic City, NJ, USA, Oct. 1-6, 2000.

+Citations(5)

103

 

A Macro Generator for Arithmetic Cores, D. Bakalis, M. Bellos, H. T. Vergos, D. Nikolos & G. Alexiou, to be presented at the XV Design of Circuits and Integrated Systems Conference (DCIS '2000), November 21 - 24 2000, Montpelier, France.

104.

 

"A Class of Easily Path Delay Fault Testable Circuits", T. Haniotakis, E. Kalligeros, D. Nikolos, G. Sidiropoulos, Y. Tsiatouhas, H.T. Vergos, Southwest Symposium on Mixed-Signal Design, February 2000, pp.165-170.

+Citations(2)

105.

 

"A Versatile Built-In Self Test Sceme for Delay Fault Testing", Y. Tsiatouhas, Th. Haniotakis, D. Nikolos, A. Arapoyanni, Design Automation and Test in Europe DATE 2000 Proceedings, pp.756.

106.

 

"Low Power BIST for Wallace Tree-based Fast Multipliers", D. Bakalis, E. Kalligeros, D. Nikolos, H. T. Vergos & G. Alexiou, in Proc. of the 1st International Symposium on Quality of Electronic Design (ISQED'00), March 20-22, 2000, San Jose, California, USA, pp. 433-438.

+Citations(6)

107.

 

"Design and Analysis of On-Chip CPU Pipelined Caches", C. Ninos, H.T. Vergos, D. Nikolos, in VLSI: Systems On A Chip, eds. by L.M. Silveira, S. Devadas and R. Reis, Kluwer Academic Publishers, 2000, pp.161-172.

108.

 

"Low Power Dissipation in BIST Schemes for Modified Booth Multipliers", D. Bakalis, H. T. Vergos, D. Nikolos, X. Kavousianos & G. Alexiou, in Proc. of 1999 International Symosium on Defect and Fault Tolerance in VLSI Systems (DFT' 99), November 1-3, 1999, Albuquerque, New Mexico, USA, pp. 121-129.

+Citations(2)

109

 

Easily Testable Carry - Save Multipliers with respect to Path Delay Faults, Th. Haniotakis, H. T. Vergos, Y. Tsiatouhas, D. Nikolos & M. Nicolaidis, 2nd Electronic Circuits and Systems Conference, September 6-8 1999, Bratislava, Slovakia, pp. 13-16. (IEEE Computer Society).

110.

 

Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers, G. Sidiropoulos, H. T. Vergos & D. Nikolos, Proceedings of the 8th Asian Test Symposium (ATS '99), November 16 -18 1999, Shanghai, China, pp. 47 - 52. (IEEE Computer Society)

+Citations(1)

111

 

"Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks", M. Bellos, D. Nikolos and H.T. Vergos, in Dependable Computing - EDCC-3 ( Lecture Notes in Computer Science, 1667) eds. J. Hlavicka and E. Maehle, Springer, 1999, pp.267-282.

112

 

Path Delay Fault Testable Modified Booth Multipliers, E. Kalligeros, H. T. Vergos, D. Nikolos, Y. Tsiatouhas & Th. Haniotakis, Proceedings of the XIV Design of Circuits and Integrated Systems Conference (DCIS '99), November 16 - 19 1999, Palma de Mallorca, Spain, pp. 301 - 306.

113.

 

"On-chip counter-based deterministic TPG with Low Heat Dissipation", Kavousianos, D. Nikolos, & S. Tragoudas, in Proc. of the 1999 Southwest Symposium on Mixed-Signal Design, April 11-13, 1999, Tucson, Arizona, USA, pp. 87-92. (IEEE Computer Society).

114.

 

"Path Delay Fault Testing of Benes Multistage Interconnection Networks", H. T. Vergos, M Bellos & D. Nikolos, In Proc. of 6th IEEE Int. Conference on Electronics, Circuits and Systems, Sept. 5-8, 1999, Pafos Cyprus, Vol 2, pp.1097-1100.

+Citations(1)

115.

 

"Modular TSC Checkers for Bose-Lin and Bose Codes", X. Kavousianos & D. Nikolos, In Proc. of 17th IEEE VLSI Test Symposium, April 25-29, 1999, Dana Point, California, pp. 354-360. (IEEE Computer Society).

+Citations(3)

116.

 

"On Path Delay Fault Testing of Multiplexer - Based Shifters", H. T. Vergos, Y. Tsiatouhas, Th. Haniotakis, D. Nikolos & M. Nicolaidis, in Proc. of Ninth Great Lakes Symposium on VLSI, Ann Arbor, Michigan, March 4-6, 1999, pp . 20-23. (IEEE Computer Society).

117.

 

"Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks", D. Nikolos, Th. Haniotakis, H. T. Vergos & Y. Tsiatouhas, in Proc. of Design, Automation and Test in Europe Conference and Exhibition, DATE-99, Germany, 9-12 March 1999, pp. 112-116. (IEEE Computer Society)

+Citations(7)

118.

 

"C-Testable One-Dimensional ILAs with respect to path delay Faults", T. Haniotakis, Y. Tsiatouhas and D. Nikolos, Proc. of 1998 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, DFT-98, Nov. 2-4 Austin, Texas, USA, pp. 155-163.

+Citations(2)

119.

"Novel Single and Double Output TSC Berger Code Checkers", X. Kavousianos, D. Nikolos 16th IEEE VLSI Test Symposium, pp.348-353, April 26-30, 1998, Monterey, California.

+Citations(11)

120.

 

"FPGA RF Framer/Deframer Unit- An Examble of a Specification Oriented design", K. Adaos, K. Platis, M. Perakis, D. Nikolos & G. Alexiou, Design Automation and Test in Europe, DATE-98, Feb. 23-26, 1998, Paris, pp. 191-194.

121.

 

"R-CBIST: An Effective RAM-based Input Vector Monitoring Concurrent BIST Technique", I . Voyiatzis, A. Paschalis, D. Nikolos & C. Xalatsis, Proc. Of International Test Conference, ITC-98, Oct. 18-23, 1998, Washington, DC, USA, pp. 918-925.

+Citations(16)

122.

 

"Design of Compact and High Speed Totally Self-Checking CMOS checkers for m-out-of-n Codes", X. Kavousianos, D. Nikolos, G. Sidiropoulos, the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'97), pp. 128-136 October 20-22, 1997, Paris, France.

+Citations(3)

123.

 

"Reconfigurable CPU Cache Memory Design: Fault Tolerance an Performance Evaluation", H. T. Vergos, D. Nikolos, P. Mitsiadis, X. Kavousianos, in Proc. of VLSI'97, IX IFIP Int. Conference On Very Large Scale Integration, VLSI 97, August 26-29, 1997, Gramado, Brazil.

+Citations(1)

124.

 

"Self-Exercising k-order Comparators Based on Built-In Current Sensing", X Brazilian Symposium on Integrated Circuit Design, August 25-27, 1997, Gramado, Brazil, X. Kavousianos, D. Nikolos, pp. 205-214.

125.

 

"FPGA implementation of a sub SDH STM/1 Framer - Deframer Uit", M. Perakis, K. Platis, K. Adaos, D. Nikolos, G. Alexiou & P. Kalnis, European Microelectronics Application Conference (EMAC-1997), 28-30 May, 1997, Bercelona, Spain, pp. 93-96.

126.

"Self-Exercising Self-Testing k-order Comparators", X. Kavousianos and D. Nikolos, 15th IEEE VLSI Test Symposium, April 27-30, 1997, Monterey, California, pp. 216-221.

+Citations(1)

127.

 

" From FPGAs to Standard Cell Based VLSI Chips ", P. Kalnis, K. Sfiris, G. Ph. Alexiou and D. Nikolos, European Design & Test Conference, Proc. of User Forum, Paris, March 17 - 20, 1997, pp. 143-146.

128.

 

" Yield - Performance tradeoffs for VLSI processors with partially good two level caches", D. Nikolos, H. T. Vergos, A. Vazaios and Voulgaris, In Proc. of 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 6-8, 1996, Boston, MA, USA, pp. 53-57.

+Citations(2)

129.

 

" On the Yield of VLSI Processors with on-chip Cache", D. Nikolos and H. T. Vergos, Proc. of Second European Dependable Computing Conference (EDCC-2), Taormina, Italy, Oct. 2-4, 1996, pp. 214-229. (Lecture Notes in Computer Science, Springer-Verlag).

+Citations(5)

130.

 

"FPGA Implementation of a Protocol Decoder-LCD Driver for a Remotely Controlled Display System", L. Athanasioy, I. Giouzelis, D. Nikolos and G. Alexiou, European Design and Test Conference 1996, Paris, March 1996, (Sponsored By the EDA Association, ACM/SIGDA and IEEE Computer Society), Proc. of User Forum, pp. 145-149.

131.

 

"An Efficient Comparative Concurrent Built-In Self-Test Technique" I. Voyiatzis, D. Nikolos, C. Halatsis and T. Haniotakis, in Proc. of Fourth Asian Test Symposium, ATS'95, pp.309-315 (Computer Society Press).

+Citations(3)

132.

 

"Testing Combinational Iterative Logic Arrays For Realistic Faults", D. Gizopoulos, D. Nikolos and A. Paschalis.Proc. of "13th IEEE VLSI Test Symposium", Princeton, 1-4 May 1995, pp. 35-40.

+Citations(2)

133.

 

"Performance Recovery in Direct-Mapped Faulty Caches via the Use of a Very Small Fully Associative Spare Cache", H.T. Vergos and D. Nikolos. in Proc of "Int. Computer Performance and Dependability Symposium", Erlangen, Germany, 24-26 April 1995, pp. 326-332.

+Citations(14)

134.

 

"Accumulator-based BIST approach for Stuck-open and Delay Fault Testing", I. Voyiatzis, A. Paschalis, D. Nikolos and K. Halatsis. Proc. of "European Design and Test Conference 1995", Paris, 6-9 March 1995, pp. 431-435.

+Citations(16)

135.

 

"C-Testable Multipliers Based on the Modified Booth Algorithm", D. Gizopoulos, D. Nikolos, A. Paschalis and P. Costarakis, in Proc. of Third Asian Test Symposium, ATS' 94, pp. 163-168, (IEEE Computer Society Press).

+Citations(6)

136.

 

"Neural network decoders for t-error correcting all unidirectional error detecting codes", N. Gaitanis, D. Nikolos, and A. Paschalis, in Proc. of FTSD-13 International Conference, Varna, June 20-22, 1990 pp. 340-345.

137.

"On t-Error Correcting and d-Unidirectional Error Detecting Codes with dt", D. Nikolos, and A. Krokos, in Proc. of FTSD-13 International Conference, Varna, June 20-22, 1990, pp. 334-339.

138.

 

"Totally Self-Checking Checkers for optimal t-Unidirectional Error Detecting Codes", D. Nikolos, A. Paschalis, T. Haniotakis, and G. Laskaris, in Proc. of FTSD-13 International Conference, Varna, June 20-22, 1990 pp. 326-331.

+Citations(1)

139.

 

"Design of Self-Testing Embedded Parity Checkers Using two input XOR gates." D. Nikolos, in Proc. of XII International Conference on Fault-Tolerant Systems and Diagnostics (FTSD) 4-7, 1989, Praha, Czechoslavakia, pp.158-162.

140.

 

"Efficient Design of TSC Checkers for 1-out-of-N Codes in MOS Transistor Implementation". G. B. Laskaris, T. N. Haniotakis, A. M.Paschalis and D. Nikolos, in Proc. of XII International Conference on Fault-Tolerant Systems and Diagnostics (FTSD), September 4-7, 1989, Praha, Czechoslavakia, pp. 163-168.

141.

 

"A Class of Error Detecting/Correcting Codes for Semiconductor Memory Systems", D. Nikolos, in Proc. of VIII International Conference on Fault-Tolerant Systems and Diagnostics, pp. 197-202, September 10-12, 1985, Katowice, Poland.

142.

 

"Design of Totally Self-Checking Comparators for Classes of n k-bit Vectors", D. Nikolos, in Proc. of VIII International Conference on Fault-Tolerant Systems and Diagnostics, pp. 203-208, September10-12, 1985, Katowice, Poland.

143.

 

"t-Error Correcting All Unidirectional Error Detecting Codes Starting from Cyclic AN Codes", D. Nikolos, N. Gaitanis and G. Philokyprou, in Proc. of Fourteenth International Conference on Fault-Tolerant Computing (FTCS), pp. 318-323 June 20-22, 1984, Kissimmee, Florida, USA. (IEEE Computer Society Press).

+Citations(18)

144.

 

"Systematic t-Error Correcting All Unidirectional Error Detecting Codes", D. Nikolos, N. Gaitanis, G.Philokyprou, in Proc. of Fault-Tolerant Computing Systems 2nd GI/NTG/GMR Conference, pp. 177-188 September 19-21, 1984, Bonn, West Germany.

+Citations(2)

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Workshops

145

 

"Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing", G.Dimitrakopoulos and D. Nikolos, 15th International Workshop on Power and Timing Modeling Optimization and Simulation, Sept. 21-23, 2005, Leuven, Belgium, pp. 308-317.

+Citations(1)

146.

 

"Vector Repetition and Modification for Peak Power Reduction in VLSI Testing" D. Bakalis, M. Bellos, D. Nikolos, X. Kavousianos, in Proc. of the 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) in Sopron, Hungary, 2005, April 13 - April 16.

147.

 

"Design of High Speed Low Power Parallel-Prefix VLSI Adders" G. Dimitrakopoulos, P. Kolovos, P. Kalogerakis and D. Nikolos, 14th International Workshop on Power and Timing Modeling Optimization and Simulation, Sept. 15-17, 2004, Santorini , Greece, pp. 248-257.

148.

 

"A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing" Y. Tsiatouhas, A. Arapoyanni, D. Nikolos and Th. Haniotakis, Proc. of 8th IEEE Int. On-Line Testing Workshop, July 8-10 2002, pp. 56-60.

+Citations(7)

149.

 

"Bit-Serial Test Pattern Generation by an Accumulator behaving as a Non-Linear Feedback Shift Register", G. Dimitrakopoulos, D. Nikolos and D. Bakalis, , Proc. of 8th IEEE Int. On-Line Testing Workshop, July 8-10 2002, pp. 152-157.

+Citations(2)

150.

 

"Concurrent detection of soft errors based on current monitoring", Y. Tsiatouhas, Th. Haniotakis, D. Nikolos and C. Efstathiou, Proc. of 7th IEEE Int. On-Line Testing Workshop, July 9-11 2001, pp. 106-110.

+Citations(5)

151.

 

"A new reseeding technique for LFSR-based test pattern generation", E. Kalligeros, X. Kavousianos, D. Bakalis and D. Nikolos, Proc. of 7th IEEE Int. On-Line Testing Workshop, July 9-11 2001, pp. 80-86.

+Citations(11)

152.

 

"EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores ", D. Bakalis, K. D. Adaos, D. Lymperopoulos, G. Ph. Alexiou and D. Nikolos, Proc. of Rapid Systems Prototyping 2001, ( RSP-01), pp. 182-187.

+Citations(1)

153.

 

A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme, H. T. Vergos, D. Nikolos, M. Bellos & C. Efstathiou, 2nd IEEE Latin American Testing Workshop (LATW 2001), February 11-14, 2001, Cancun, Mexico, pp. 242 - 247.

154.

"A Compact Built-In Current Sensor for Iddq Testing", Y.Tsiatouhas, Th.Haniotakis and D.Nikolos, Proc. of 6th IEEE Int. On-Line esting Workshop, July 3-5 2000, Mallorca, Spain, pp. 95-99.

+Citations(2)

155.

 

"A New Scheme for Effective IDDQ Testing in Deep Submicron", Y. Tsiatouhas, Y Moisiadis, Th. Haniotakis, D. Nikolos, IEEE International Workshop on Defect Based Testing DBT, April 2000, pp. 9-14.

+Citations(4)

156.

 

"On-Line Path Delay Fault Testing of Omega MINs", M. Bellos, E. Kalligeros, D. Nikolos & H. T. Vergos, in Proc of the 5th IEEE Int. On-Line Testing Workshop, July 5-7, 1999, Rhodes, Greece, pp.133-137.

157.

 

" Novel Domino-CMOS Strongly Code Disjoint and Strongly Fault Secure 1-out-of-3 and 2-out-of-3 Code Checkers," Th. Haniotakis, Y. Tsiatouhas, C. Efstathiou &D. Nikolos, in Proc of the 5th IEEE Int. On-Line Testing Workshop, July 5-7, 1999, Rhodes, Greece, pp.174-178.

+Citations(2)

158.

" On low Power BIST for Carry Save Array Multipliers", D. Bakalis & D. Nikolos, in Proc. of the 5th IEEE Int. On-Line Testing Workshop, pp. 86-90, July 5-7, 1999, Rhodes, Greece.

159.

 

"Development of a Reusable E1 Tranceiver Suitable for Rapid Prototyping", A. Vasilliou, K. Gounaris, K. Adaos, D. Mitsainas, G. Alexiou & D. Nikolos, in Proc. of the Int. Workshop on Rapid System Prototyping, RSP'99, June 16-18, 1999, Univ. of South Florida, Tampa, Florida, pp. 21-26.

+Citations(1)

160.

 

"Exhaustive and pseudo-exhaustive arithmeic built-in two pattern test generation for datapaths", I Voyiatzis, A. Paschalis, D. Nikolos 7 C. Halatsis, 4th IEEE International On-Line Testing Workshop, pp. 90-94, July 6-8, 1998, Capri, Italy.

161.

"Novel TSC Checkers for Bose-Lin and Bose Codes", X. Kavousianos & D. Nikolos, 4th IEEE International On-Line Testing Workshop, pp. 172-176, July 6-8, 1998, Capri, Italy.

+Citations(1)

162.

"Efficient Highly Testable Borden Code Checkers", D. Nikolos & X. Kavousianos, IEEE European Test Workshop, pp. 246-250, May 1998, Spain.

+Citations(4)

163.

 

"A Totally Self-Checing Error Correcting/Detecting Circuit for a Class of SEC/DED/AUED Codes", D. Nikolos, X. Kavousianos, 3rd IEEE International On-Line Testing Worshop, pp. 218-222, July 7-9, 1997, Crete, Greece.

164.

"Optimal Self - Testing Embedded Two - Rail Checkers", D. Nikolos, 2nd IEEE Intern. On-Line Testing Workshop Biarritz, France, July 8-10, 1996, pp. 154-157.

+Citations(1)

165.

 

"On The Testability Of Low - Power Optimized Circuits", M. Perakis, H. T. Vergos and D. Nikolos, 2nd IEEE Intern. On-Line Testing Workshop Biarritz, France, July 8-10, 1996, pp. 154-157.

166.

 

"Reconfigurable CPU Cache Memory Design: Fault Tolerance and Performance Evaluation, D. Nikolos, H. T. Vergos & P. Mitsiadis, 1st IEEE International On - Line Testing Workshop, July 4-6, 1995, Nice, France.

167.

 

"Data Busses", K. Dagakis, P. Kostarakis, D. Nikolos and A. Paschalis, European Conference on Conformance Testing & Certification in Information Technology & Tellecomunications, 13-15 June,1990, Brussels.

168.

 

"A Fault Tolerant Dynamic RAM Memory System", D. Nikolos, P. Kostarakis and A. M. Paschalis, in Proc. of the First European Workshop on Fault Diagnostics, Reliability and Related Knowledge-Based Approaches, August 31 - September 3, 1986, Rhodes, Greece, pp.301-308. (D. Reidel Publishing Company.)

169.

 

"Efficient Design of Totally Self-Checking Checkers for All Separate Low Cost Arithmetic codes", D. Nikolos, A. M. Paschalis and G. Philokyprou, in Proc. of First European Workshop on Fault Diagnostics, Reliability and Related Knowledge-Based Approaches, August 31 -September 3, 1986, Rhodes, Greece, pp.345-356. (D. Reidel Publishing Company).

170.

 

"Efficient Modular Design of TSC Checkers for M-out-of-2M Codes", A. Paschalis, D. Nikolos and C. Halatsis, in Proc. of Aegean Workshop of Computing VLSI Algorithms and Architectures, July 8-11,1986, Loutraki, Greece, pp.144-155. (Springer-Verlag ).

171.

 

"Single error correcting, all unidirectional error detecting code based on cyclic AN codes", D. Nikolos, N. Gaitanis, G. Philokyprou, Seventh Balkan Congress of Mathematicians, 19-23 December 1983, Athens, Greece.

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Fast Abstracts

172.

 

G. Dimitrakopoulos, X. Kavousianos, and D. Nikolos, "Software-Based Self-testing of Microprocessors by Exploiting a Virtual Scan Path", in the Supplement of the 4th European Dependable Computing Conference (EDCC-4), Toulouse, France, October 2002, pp. 23-24.

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Greek Symposiums

173.

"Eia Ee?aeaaooeeu Oyoocia Eiaaua?o AeaiooiUoui Aieei?o", A. Neeieuo, A. Toeaoiy?ao eae E. McoUoio, 4i Daiaee?iei ooiYanei Decnioinee?o, 16-18 Aaeaian?io 1993, pp. 165-175.

174.

 

"Microprogrammable Educational System for Computer Architecture Laboratories", A. Neeieuo, A. Aaaae?o, I. Kaeaiaoeaiuo eae E. Kaeai?iyeao, 4i Daiaee?iei ooiYanei Decnioinee?o, 16-18 Aaeaian?io 1993, pp. 141-152.

175.

 

"Ta?ieeYo eaoaiii?o a?aianaaoo?i oa ?aneaUeeii aaianiaeaiyo aei?Yoaooco aaaiiYiui ia aiaieiiaee? ?anaeece?a." N. OeYooao, A. Neeieuo eae D. AaunaeUaco, 3i Daiaee?iei ooiYanei Decnioinee?o, 28-30 Mauio 1991, pp.459-470.

176

 

"Eyeiea ?naaiaoi?ie?oeiie oooociaoeei? t-EA/OOEA e?aeeao.", A. Neeieuo, A. Knueio eae A. Oeeiey?nio. 2i Daiaee?iei ooiYanei ?ecnioinee?o, Eaooaeii?ec 4-6 Niaian?io 1988, pp. 219-228.

177

 

"DanUeecec aeoYeaoc anuoa?ien?oaui aUoaui aaaiiYiui.", A. Oeeiey?nio, K. XaeUooco, M. Xaoau?ioeio, A. Kion?ico, A. Neeieuo, N. OeYooao, D. Aan?aco eae M. O?ceei?iyeio. 2i Daiaee?iei ooiYanei ?ecnioinee?o,Eaooaeii?ec 4-6 Niaian?io 1988, pp.100-110.

178

 

"Aeauneeiie aea oci ?naaiaoi?i?coc ?nUiaui oco o?aoeae?o Ueaaanao oa ?aneaUeeii aaianiaeaiyo aei?Yoaooco aaaiiYiui.", A. Neeieuo eae M. Xaoau?ioeio, 2i Daiaee?iei ooiYanei ?ecnioinee?o, Eaooaeii?ec 4-6 Niaian?io 1988, pp. 39-50.

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Book Reviews

179

 

Digital Logic Testing and Simulation, by Alexander Miczo, second edition, Wiley Interscience, D. Nikolos, Instrumentation & Measurement Magazine, IEEE, Volume: 7, Issue:2, June 2004, Pages:78 - 79

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Patents

180

High-Speed Parallel-Prefix Modulo 2n-1 Adders, L. Kalampoukas, D. Nikolos, C. Efstathiou, H. T. Vergos & J. Kalamatianos, pending World Patent, WO 02/08885 A1.

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